Sampling clock adjustment for an analog to digital converter of a receiver
AssigneeeTopus Technology Inc.
InventorYu Kou
Life of this patent
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Abstract
A receiver for high speed communications. The receiver includes an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock. A finite impulse response filter generates at least one filtered input signal based on the digital input signal. A data decision circuit recovers data based on the filtered input signal. The filtered input signal and the recovered data can be provided to a feedback loop to determine a timing error of the sampling clock, which is then used to generate the sampling clock.
Claims16
A receiver comprising:
- an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock;
- a finite impulse response filter to generate at least one filtered input signal based on the at least one digital input signal;
- a data decision circuit to generate recovered data based on the at least one filtered input signal;
- and
- a feedback loop coupled to receive the at least one filtered input signal and to receive the recovered data and to generate the sampling clock based on the at least one filtered input signal and the recovered data, the feedback look comprising:
- a signal reconstruction circuit to generate at least one reconstructed input signal corresponding to a reconstructed version of the at least one filtered input signal based on the recovered data;
- and
- a timing error circuit to generate at least one timing error signal indicative of a difference between the at least one filtered input signal and the at least one reconstructed input signal;
- and
- a clock generator circuit to generate the sampling clock based on the at least one timing error signal.
A receiver comprising:
- an analog to digital converter to convert an analog input signal into at least one digital input signal at timings controlled by a sampling clock;
- a finite impulse response filter to generate at least one filtered input signal based on the at least one digital input signal;
- a data decision circuit to generate recovered data based on the at least one filtered input signal;
- and
- a feedback loop coupled to receive the at least one filtered input signal and to generate the sampling clock based on the at least one filtered input signal, the feedback loop comprising:
- a timing error look up table that references the at least one filtered input signal and the recovered data to values for at least one timing error signal;
- and
- a clock generator to generate the sampling clock based on the at least one timing error signal.
A method of operation in a receiver, the method comprising:
- converting an analog input signal into at least one digital input signal at timings controlled by a sampling clock;
- generating at least one filtered input signal based on the at least one digital input signal using a finite impulse response filter;
- generating recovered data based on the at least one filtered input signal;
- receiving the at least one filtered input signal and the recovered data at a feedback loop;
- generating the sampling clock with the feedback loop based on the at least one filtered input signal and the recovered data, wherein generating the sampling clock comprises:
- generating at least one reconstructed input signal corresponding to a reconstructed version of the at least one filtered input signal based on the recovered data;
- and
- generating at least one timing error signal indicative of a difference between the at least one filtered input signal and the at least one reconstructed input signal;
- and
- generating the sampling clock based on the at least one timing error signal.
Dependencies are inferred from the claim text.