Memory device and memory system
AssigneeSamsung Electronics Co., Ltd.
InventorsMan-keun Seo, Jun-jin Kong, Kyoung-Lae Cho
Life of this patent
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Abstract
A memory device and a memory system, the memory system including a data compressor for generating compressed data by compressing program data in a first unit, and an error correction block generator for dividing the compressed data in a second unit to obtain a plurality of pieces of normal data, and generating error correction blocks for correcting errors of the plurality of pieces of normal data, wherein each of the error correction blocks comprises the normal data, invalid data having a size corresponding to the size of the normal data, and parities for the normal data and the invalid data.
Claims23
A method of operating a nonvolatile memory system, the method comprising:
- compressing input data input from a host into a compressed data of a first unit, via a nonvolatile memory controller;
- dividing the compressed data into at least two pieces of divided data, via the nonvolatile memory controller;
- generating at least two pieces of combined data by combining invalid data with each of the at least two pieces of divided data, via the nonvolatile memory controller, wherein each of the at least two pieces of combined data have an equal size;
- generating corresponding parity data for each of the at least two pieces of combined data, via the nonvolatile memory controller;
- and
- transmitting the at least two pieces of combined data and the corresponding parity data for each of the at least two pieces of combined data to a nonvolatile memory, via the nonvolatile memory controller.
An error detection and correction method of a nonvolatile memory system, comprising:
- compressing data corresponding to an integer N, equal to or greater than 2, number of logic pages of data input from a host into compressed data, via a nonvolatile memory controller;
- dividing the compressed data into at least two pieces of valid data, via the nonvolatile memory controller;
- generating at least two pieces of combined data by combining invalid data with each of the at least two pieces of valid data, via the nonvolatile memory controller, wherein each of the at least two pieces of combined data have an equal size;
- generating corresponding parity data for each of the at least two pieces of combined data, via the nonvolatile memory controller;
- forming at least two error correction blocks, each of the error correction blocks comprising one of the at least two pieces of combined data and the corresponding parity data for the one of the at least two pieces of combined data, via the nonvolatile memory controller;
- and
- transmitting the at least two error correction blocks to one physical page address of a nonvolatile memory, via the nonvolatile memory controller.
A method of operating a memory system, the method comprising:
- compressing input data into a compressed data of a first unit, via a data compressor of the memory system;
- dividing the compressed data into at least two pieces of divided data, via an error correction block generator of the memory system;
- generating at least two pieces of combined data by combining invalid data with each of the at least two pieces of divided data, via the error correction block generator, wherein each of the at least two pieces of combined data have an equal size;
- generating corresponding parity data for each of the at least two pieces of combined data, via the error correction block generator;
- and
- transmitting the at least two pieces of combined data and the corresponding parity data for each of the at least two pieces of combined data to a memory cell array of the memory system.
Dependencies are inferred from the claim text.