Hybrid pipelined analog-to-digital converter

A method of converting an analog input signal to a digital output signal, the method comprising:

• generating a first digital signal corresponding to a most-significant-bits (MSB) portion of the digital output signal using a first analog to digital converter (ADC) stage, the first ADC stage comprises a successive approximation register (SAR);
• generating a residual voltage corresponding to a voltage value difference between the analog input signal and the first digital signal;
• and
• converting the residual voltage into a plurality of second digital signals corresponding to a least-significant-bits (LSB) portion of the digital output signal using a second ADC stage coupled with the first ADC stage, the second ADC stage comprises a plurality of time-to-digital converter (TDC) cells coupled in series,
• wherein the TDC cells of the plurality of TDC cells each generate a second digital signal of the plurality of second digital signals.

An analog-to-digital converter (ADC) comprising:

• a first ADC stage configured to convert a received analog input signal into a first digital signal corresponding to a most-significant-bits (MSB) portion of a digital output signal, and to generate a residual voltage corresponding to a difference between a voltage value of the analog input signal and the first digital signal, the first ADC stage comprising:
• a successive approximation register (SAR);
• a capacitor array comprising a plurality of capacitors, the capacitors of the capacitor array comprising a first side coupled with a first node, and a second side configured to be selectively coupled with one of the analog input signal, a first reference signal or a second reference signal;
• a first comparator comprising a first input coupled with the first node and a second input coupled with one of the first reference signal, the second reference signal, or a third reference signal, the first comparator is configured to generate the residual voltage;
• and
• a second comparator comprising a third input coupled with the first comparator and a fourth input coupled with the second reference signal, the second comparator is configured to compare the residual voltage with the second reference signal and to output a control signal based on the comparison, the control signal comprising the residual voltage;
• a second ADC stage coupled with the first ADC stage, the second ADC stage comprises a plurality of time-to-digital converter (TDC) cells coupled in series, the second ADC stage is configured to convert the residual voltage into a plurality of second digital signals generated by the TDC cells of the plurality of TDC cells, the second digital signals of the plurality of second digital signals correspond to a least-significant-bits (LSB) portion of the digital output signal;
• and
• a digital error correction unit configured to generate the digital output signal based on the first digital signal and the second digital signals of the plurality of second digital signals,
• wherein the SAR is configured to control the selective coupling of the second sides of the capacitors of the capacitor array with the analog input signal, the first reference signal or the second reference signal based on the residual voltage generated by the first comparator.