Redundancy scheme for flash assisted successive approximation register (SAR) analog-to-digital converter (ADC)
AssigneeSamsung Electronics Co., Ltd.
InventorAshutosh Verma
Life of this patent
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Abstract
Apparatuses, systems, and methods for Analog-to-Digital Converters (ADCs) are described. In one aspect, an ADC is described which uses a Flash-assisted ADC and a Successive Approximation Register (SAR) to provide digital approximations of an input analog voltage to a Capacitor Digital-to-Analog Converter (DAC), which generates a voltage from the digital approximations. The two voltages are compared and the comparison value used as the input for the SAR. After successive approximations, a digital combiner generates the digital conversion value from the outputs of the Flash-assisted ADC and the SAR. In one aspect, the bit cycles required for conversion are reduced by using redundancy and recombination.
Claims20
An Analog-to-Digital Converter (ADC), comprising:
- a Capacitor Digital-to-Analog Converter (DAC) which receives digital approximations of an input analog voltage as input and generates an analog voltage based on the digital approximations as output, comprising:
- a first DAC related to Most Significant Bits (MSBs) of the binary output, which uses thermometer coding, receives first digital approximations and generates a corresponding first analog voltage, comprising:
- a plurality of capacitances of equal value Ccommon and one or more capacitances of a different value Cred;
- and
- a second DAC related to Least Significant Bits (LSBs) of the binary output, which is non-binary, receives second digital approximations and generates a corresponding second analog voltage, comprising:
- a plurality of capacitances equalling the sum of binary capacitances of the LSBs subtracted by the one or more capacitances of a different value Cred;
- a comparator which generates a comparator value indicating the input analog voltage subtracted by the first analog voltage generated by the first DAC;
- a Successive Approximation Register (SAR) which receives the comparator value and generates the second digital approximations which are input to the second DAC, wherein the SAR repeats this process in successive approximation;
- a Flash-assisted ADC which receives the input analog voltage and generates first digital approximations which are input into the first DAC;
- and
- a digital combiner which receives the first digital approximations from the Flash-assisted ADC and the second digital approximations from the SAR and generates a binary output representing the conversion of the input analog voltage.
A broadband modem chip, comprising:
- an Analog-to-Digital Converter (ADC), comprising:
- a Capacitor Digital-to-Analog Converter (DAC) which receives digital approximations of an input analog voltage as input and generates an analog voltage based on the digital approximations as output, comprising:
- a first DAC related to Most Significant Bits (MSBs) of the binary output, which uses thermometer coding, receives first digital approximations and generates a corresponding first analog voltage, comprising:
- a plurality of capacitances of equal value Ccommon and one or more capacitances of a different value Cred;
- and
- a second DAC related to Least Significant Bits (LSBs) of the binary output, which is non-binary, receives second digital approximations and generates a corresponding second analog voltage, comprising:
- a plurality of capacitances equalling the sum of binary capacitances of the LSBs subtracted by the one or more capacitances of a different value Cred;
- a comparator which generates a comparator value indicating the input analog voltage subtracted by the first analog voltage generated by the first DAC;
- a Successive Approximation Register (SAR) which receives the comparator value and generates the second digital approximations which are input to the second DAC, wherein the SAR repeats this process in successive approximation;
- a Flash-assisted ADC which receives the input analog voltage and generates first digital approximations which are input into the first DAC;
- and
- a digital combiner which receives the first digital approximations from the Flash-assisted ADC and the second digital approximations from the SAR and generates a binary output representing the conversion of the input analog voltage.
An Analog-to-Digital Converter (ADC) for converting input analog to an N-bit binary output, divided into Most Significant Bits (MSBs) and Least Significant Bits (LSBs), where nMSB is the number of bit positions in the MSBs and ML is the lowest bit position in the MSBs, and LH is the highest bit position in the LSBs, comprising:
- a Capacitor Digital-to-Analog Converter (DAC) comprising 2N capacitance units/LSBs, divided into:
- a thermometer coded DAC comprising:
- 2nMSB−2 capacitances of equal value Ccommon, where Ccommon=2ML capacitance units/LSBs;
- and
- 2 capacitances of value Cred;
- and
- a non-binary DAC comprising:
- LH+1 capacitances, as well as a termination capacitance equalling one capacitance unit/LSB;
- a Flash-assisted ADC which receives the input analog voltage and generates a 2nMSB bit thermometer coded input for the first DAC, where the lowest bit is for one of the capacitances of value Cred, the next 2nMSB−2 bits are for the capacitances of equal value Ccommon, and the highest bit is for the other capacitance of value Cred;
- a Successive Approximation Register (SAR) which generates a LH+1 bit input for the non-binary DAC;
- and
- a digital combiner which receives the 2nMSB bit thermometer coded output of the Flash-assisted ADC and, after successively approximated over LH+1 cycles, the LH+1 bit output of the SAR and generates a binary output representing the conversion of the input analog voltage,
- wherein the 2nMSB+2 capacitances of the thermometer coded DAC and the LH+1 capacitances, as well as a termination capacitance equalling one capacitance unit/LSB, in the non-binary DAC equal a total value of 2N capacitance units/LSBs.
Dependencies are inferred from the claim text.