Circuit for symbol timing synchronization

A timing synchronization circuit for a digital receiver structure, comprising:

• a timing error detection module comprising a phase difference calculation unit arranged for calculating a phase difference between incoming samples of a digital data stream, and a timing error estimator arranged for determining a plurality of timing error estimates based on the calculated phase difference, for generating an averaged timing error estimate based on the plurality of timing error estimates, and for generating, based on a comparison of the plurality of timing error estimates or the averaged timing error estimate with a first threshold, a signal indicative of timing error detection;
• and
• a timing error control module arranged for receiving the signal indicative of timing error detection, for evaluating a number of received signals indicative of timing error detection, and for outputting, responsive to a comparison of the number of received signals indicative of timing error detection with a second threshold, a sampling adjustment command for adjusting sampling instants applied for obtaining the digital data stream.