Frequency dividing circuit and phase synchronization circuit
AssigneeSony Corporation
InventorsYusuke Tanaka, Kenji Komori
Life of this patent
Estimating the term…
Abstract
A frequency dividing circuit includes: a mode selection section configured to determine an exclusive OR of a first clock signal and a first signal and output the exclusive OR as a second signal in a first operation mode, and to output the first clock signal as the second signal in a second operation mode; and a clock generation section configured to generate and output a second clock signal, based on the second signal and the second clock signal, and to output one of the second clock signal and a third clock signal, as the first signal, the third clock signal having a phase same as a phase of the second clock signal.
Claims8
A frequency dividing circuit comprising:
- a mode selection section configured to determine an exclusive OR of a first clock signal and a first signal and output the exclusive OR as a second signal in a first operation mode, and to output the first clock signal as the second signal in a second operation mode;
- and
- a clock generation section configured to generate and output a second clock signal, based on the second signal and the second clock signal, and to output one of the second clock signal and a third clock signal, as the first signal, the third clock signal having a phase same as a phase of the second clock signal.
A phase synchronization circuit comprising:
- a phase frequency detector configured to compare a phase of an input clock signal with a phase of a feedback clock signal;
- an oscillation circuit configured to generate a first clock signal based on a comparison result of the phase frequency detector;
- a first frequency dividing circuit configured to divide a frequency of the first clock signal to generate a second clock signal;
- and
- a second frequency dividing circuit configured to divide a frequency of the second clock signal to generate the feedback clock signal, wherein
- the first frequency dividing circuit includes
- a mode selection section configured to determine an exclusive OR of the first clock signal and a first signal and output the exclusive OR as a second signal in a first operation mode, and to output the first clock signal as the second signal in a second operation mode, and
- a clock generation section configured to generate and output the second clock signal, based on the second signal and the second clock signal, and to output one of the second clock signal and a third clock signal, as the first signal, the third clock signal having a phase same as a phase of the second clock signal.
Dependencies are inferred from the claim text.