Programmable logic circuit and nonvolatile FPGA

A programmable logic circuit, comprising:

• a first programmable device with a first terminal and a second terminal, a resistance of the first programmable device being changeable from a high resistance to a low resistance;
• a second programmable device with a third terminal and a fourth terminal, a resistance of the second programmable device being changeable from a high resistance to a low resistance;
• a first wiring line to which the first terminal of the first programmable device is connected;
• a second wiring line to which the third terminal of the second programmable device is connected;
• a third wiring line to which the second terminal of the first programmable device and the fourth terminal of the second programmable device are connected;
• and
• a fuse element of which one terminal is connected to the third wiring line,
• wherein each programmable device is a MOS transistor in which a source and a drain are connected to each other, the source of the first programmable device is one of the first terminal and the second terminal, a gate of the first programmable device is the other, the source of the second programmable device is one of the third terminal and the fourth terminal, and a gate of the second programmable device is the other.

A programmable logic circuit comprising:

• a plurality of cells arranged in a matrix form with rows and columns, each cell including a programmable device with a first terminal and a second terminal, a resistance of the programmable device being changeable from a high resistance to a low resistance;
• a plurality of first wiring lines each corresponding to one of the columns of the cells, and being connected to the first terminals of the programmable devices of the cells in the corresponding one of the columns;
• a plurality of second wiring lines each corresponding to one of the rows of the cells, and being connected to the second terminals of the programmable devices of the cells in the corresponding one of the rows;
• a plurality of fuse elements each corresponding to one of the second wiring lines, one terminal of each fuse element being connected to the corresponding one of the second wiring lines;
• and
• a write circuit configured to select a first wiring line among the plurality of first wiring lines and to select a second wiring line among the plurality of second wiring lines, and to apply a first voltage to the selected first wiring line and a second voltage to the selected second wiring line.