Reconfigurable logic gates using chaotic dynamics

A method for chaos computing, the method comprising:

• converting, at an encoding circuit block, a plurality of digital inputs to an analog output, the plurality of digital inputs comprising at least one data input and at least one control input;
• converting, at a bias voltage generating circuit block, a plurality of binary control inputs to a bias voltage;
• converting, by at least one chaotic circuit block, an input signal to an output signal by feeding the output signal to the at least one chaotic circuit as the input signal at each iteration;
• determining the output signal by performing circuit operations comprising at least one of:
• changing the at least one control input of the encoding circuit block;
• changing a number of the each iteration at the at least one chaotic circuit block;
• or
• changing the plurality of binary control inputs at the bias voltage generating circuit block;
• and
• comparing, at a threshold circuit block, the output signal with a predetermined threshold to generate a digital signal.