Switching regulator with controllable slew rate
AssigneeAllegro MicroSystems, LLC
InventorJoshua Wibben
Life of this patent
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Abstract
A driver circuit for driving a switching transistor having a control terminal responsive to a switching control signal includes a plurality of driver stages, each having a control input responsive to a respective driver control signal and an output coupled to the output of the other driver stages and to the control terminal of the switching transistor. At least one of the driver control signals has an on time that is delayed with respect to the other driver control signals. In an embodiment, at least two driver stages are on during a slew time interval.
Claims21
A driver circuit for driving a switching transistor having a control terminal responsive to a switching control signal, comprising:
- a plurality of driver stages, each having a control input responsive to a respective driver control signal having an on time during which the driver stage is on and an off time during which the driver stage is off and having an output coupled to the output of the other ones of the plurality of driver stages and to the control terminal of the switching transistor, wherein at least one of the plurality of driver control signals has an on time that is delayed with respect to an on time of another one of the plurality of driver control signals, wherein the switching transistor has a slew time interval that commences when a Miller plateau of the switching transistor is reached and terminates when a source to drain voltage of the switching transistor reaches a final voltage level and wherein at least two of the driver stages are on during the slew time interval;
- and
- a driver control signal generator configured to generate the plurality of driver control signals, wherein each of the driver control signals is responsive to a slew time interval indication signal indicative of commencement of the slew time interval.
A method of controlling a switching transistor of a converter comprising:
- providing a plurality of driver stages, each having a respective control input and an output coupled to the output of other ones of the plurality of driver stages and to the switching transistor, wherein the switching transistor has a slew time interval that commences when a Miller plateau of the switching transistor is reached and terminates when a source to drain voltage of the switching transistor reaches a final voltage level;
- generating a plurality of driver control signals for coupling to the plurality of driver control inputs in response to a slew time interval indication signal indicative of commencement of the slew time interval,
- delaying turning on at least one of the plurality of driver stages relative to at least one other one of the plurality of driver stages, and
- turning on at least two of the driver stages during the slew time interval.
Dependencies are inferred from the claim text.