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US 9,425,773 B2Granted
Digital control ring oscillator and method of assembling same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorTsung-Hsien Tsai
Life of this patent
Estimating the term…
Abstract
A digital control ring oscillator (DCO) generally comprises a first delay element and at least one second delay element that is coupled to the first delay element, wherein each of the first and second delay elements are disposed laterally with respect to one another in a first direction and include at least one cell. The cell includes a plurality of transistors arranged in at least one stack.
Claims20
A circuit comprising:
- a first delay element;
- and
- at least one second delay element coupled to the first delay element, wherein each of the first and second delay elements are disposed laterally with respect to one another in a first direction and each comprise at least one cell comprising a plurality of transistors arranged in at least two tiers of at least one stacked 3D integrated circuit, the at least two tiers arranged physically one above the other.
An integrated circuit comprising:
- a digital control ring oscillator comprising:
- a first delay element;
- and
- at least one second delay element coupled to the first delay element, wherein each of the first and second delay elements are disposed laterally with respect to one another in a first direction and comprise at least one cell comprising:
- a first plurality of transistors of a first type arranged in at least two tiers of at least one first stack of at least one stacked 3D integrated circuit;
- and
- a second plurality of transistors of a second type arranged in at least two tiers of at least one second stack of the at least one stacked 3D integrated circuit, the at least two tiers arranged physically one above the other in a direction normal to a plane of a substrate of the integrated circuit, wherein the first and second pluralities of transistors of the first and second types are coupled together.
4 more elements
A method comprising:
- receiving a first signal at a gate of a first transistor of a first type;
- receiving a second signal that is complementary to the first enablement signal at a gate of a first transistor of a second type;
- and
- outputting at least one inverted signal in response to receiving a signal at a gate of a second transistor of the first type and at a gate of a second transistors of the second type,
- wherein the first and second transistors of the first type are arranged in at least two tiers of a first stack within a stacked 3D integrated circuit, the at least two tiers of the first stack arranged physically one above the other, the first and second transistors of the second type are arranged in at least two tiers of a second stack within the stacked 3D integrated circuit, the at least two tiers of the second stack arranged physically one above the other.
2 more elements
Dependencies are inferred from the claim text.