Doped oxide dielectrics for resistive random access memory cells

A method of fabricating a memory cell, the method comprising:

• forming a first layer using atomic layer deposition (ALD) over a layer comprising titanium nitride and operable as a first electrode,
• wherein the first layer comprises hafnium oxide and titanium oxide arranged into a nanolaminate of sub-layers comprising hafnium oxide and sub-layers comprising the titanium oxide,
• wherein a concentration ratio of hafnium oxide to titanium oxide in the first layer is between about 3 and 7, and
• wherein a thickness of the first layer is between about 20 Angstroms and 100 Angstroms;
• annealing the first layer in a first environment comprising molecular oxygen at a temperature of 500° C. for about 1 minute;
• after annealing the first layer in the first environment, forming a second layer over the first layer,
• wherein the second layer comprises silicon oxide and wherein a thickness of the second layer is between about 5 Angstroms and 20 Angstroms;
• after forming the second layer, forming a third layer over the second layer,
• the third layer comprising tantalum nitride and operable as a second electrode;
• and
• annealing the first layer, the second layer, and the third layer in a second environment comprising molecular nitrogen at a temperature of about 750° C. for about 1 minute,
• wherein, after annealing, distribution of hafnium oxide and distribution of titanium oxide within the first layer are both uniform.