Low voltage transistor and logic devices with multiple, stacked piezoelectronic layers

A piezoelectronic logic device, comprising:

• a first piezoelectric transistor (PET) device and a second PET device, the first PET device and the second PET device each having a first PE material layer, a second PE material layer, and a piezoresistive (PR) material layer arranged in a stacked configuration, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the first and second PE material layers by way of an applied pressure to the PR material layer by the first and second PE material layers;
• wherein the first and second PE material layers of the first PET device have a smaller cross sectional area than the first and second PE material layers of the second PET device such that a voltage drop across the first and second PE material layers of the first PET device creates a first pressure in the PR material layer of the first PET device that is smaller with respect to a second pressure in the PR material layer of the second PET device created by the same voltage drop across the first and second PE material layers of the second PET device.