Vertical memory device and method for making thereof

A method comprising:

• providing a semiconductor substrate;
• providing a top layer on the semiconductor substrate, thereby forming a semiconducting substrate comprising the semiconductor substrate and the top layer, wherein the top layer comprises a first type of dopants;
• providing a stack of layers on the semiconducting substrate, wherein the stack of layers comprises at least a first dielectric layer, a conductive layer formed on the first dielectric layer, and a second dielectric layer formed on the conductive layer;
• providing a hole in the stack of layers, thereby exposing a portion of the semiconducting substrate;
• providing a gate dielectric at least at opposing sidewall surfaces that define the hole;
• providing a substantially undoped semiconducting material in the hole, thereby forming a middle region of a vertical memory device in the hole;
• using an anneal to form a bottom region of the vertical memory device in the hole, wherein the bottom region is adjacent to the top layer of the semiconducting substrate and the middle region and comprises dopants of the first type of dopants;
• providing a first doped semiconducting material on the substantially undoped semiconducting material in the hole, thereby forming a first top region of the vertical memory device in the hole, wherein the first doped semiconducting material comprises a second type of dopants different from the first type of dopants;
• and
• providing a second doped semiconducting material over the first doped semiconducting material, thereby forming a second top region of the vertical memory device in the hole, wherein the second doped semiconducting material comprises the first type of dopants.

A vertical memory device comprising:

• a semiconducting substrate;
• a vertical semiconducting region formed on the semiconducting substrate, wherein the vertical semiconducting region comprises a source region, a drain region, and a channel region positioned between the source region and the drain region;
• a horizontal stack formed adjacent to the vertical semiconducting region, wherein the horizontal stack comprises a first dielectric layer, a second dielectric layer, and a conductive layer positioned between the first dielectric layer and the second dielectric layer, and wherein the conductive layer is a conductive gate layer;
• and
• a charge-trapping layer formed at least between the vertical semiconducting region and the conductive gate layer,
• wherein at least one of the source region or the drain region comprises (i) a first region approximate to and extending across an entire width of the channel region, and comprising a first type of dopants and (ii) a second region adjacent to the vertical semiconducting region and the first region, and extending across an entire width of the channel region, and comprising a second type of dopants different than the first type of dopants,
• wherein one of the source region or the drain region includes the first region comprising the first type of dopants and the second region comprising the second type of dopants;
• and the other of the source region or the drain region comprising the first type of dopants with no substantial amount of the second type of dopants.