Electrically programmable and eraseable memory device

A memory device comprising:

• a substrate;
• a tunneling layer provided over the substrate;
• a floating gate provided over the tunneling layer;
• a dielectric provided over the floating gate and comprising a first insulating layer, a second insulating layer, and a third insulating layer,
• the first insulating layer provided over the floating gate and comprising silicon dioxide,
• the second insulating layer provided over the first insulating layer and comprising silicon oxynitride, and
• a third insulating layer provided over the second insulating layer and comprising silicon nitride;
• a control gate provided over the dielectric and connected to a positive voltage source;
• a source and a drain provided in the substrate,
• wherein the source and the drain are in contact with opposite sides of a bottom surface of the tunneling layer;
• a plurality of electron holes having sufficient energy to overcome a valence energy level of the first and third insulating layers and operable to travel through the first insulating layer, the second insulating layer, and the third insulating layer,
• the plurality of electron holes being generated in the control gate in response to receiving the positive voltage at the control gate;
• and
• a plurality of barriers corresponding to the first insulating layer, the second insulating layer, and the third insulating layer,
• wherein the silicon oxynitride layer comprises alternating silicon nitride and silicon dioxide monolayers,
• wherein the positive voltage source is also connected to the drain, and
• wherein the source is connected to ground and allowing the substrate to float during an electrical erase operation,
• wherein the positive voltage of the positive voltage source includes sufficient magnitude to eliminate a barrier corresponding to the second insulating layer, and to reduce the plurality of barriers corresponding to the first and third insulating layers, and
• wherein a conductive energy level of the second insulating layer is higher than a conductive energy level of the third insulating layer.