Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same

An integrated circuit comprising:

• a semiconductor substrate;
• a first fin and a second fin adjacent to each other extending from the semiconductor substrate, wherein the first fin has a first upper section and the second fin has a second upper section;
• a first epi-portion overlying the first upper section and a second epi-portion overlying the second upper section, wherein the first and second epi-portions are spaced apart from each other;
• a first silicide layer overlying the first epi-portion and a second silicide layer overlying the second epi-portion, wherein the first and second silicide layers are spaced apart from each other to define a lateral gap;
• a dielectric spacer formed of a dielectric material and spanning the lateral gap;
• and
• a contact-forming material overlying the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer, wherein the first epi-portion is a first diamond-shaped/cross-section epi-portion having a first upper surface and a first lower surface and the second epi-portion is a second diamond-shaped/cross-section epi-portion having a second upper surface and a second lower surface, wherein the first silicide layer is disposed along the first upper and lower surfaces of the first diamond-shaped/cross-section epi-portion and the second silicide layer is disposed along the second upper and lower surfaces of the second diamond-shaped/cross-section epi-portion, and wherein the first and second silicide layers have lower portions that overlie the first and second lower surfaces of the first and second diamond-shaped/cross-section epi portions, and wherein the integrated circuit further comprises:
• a first dielectric film overlying the lower portion of the first silicide layer;
• and
• a second dielectric film overlying the lower portion of the second silicide layer, wherein the dielectric spacer is integrally formed with the first and second dielectric films, and wherein the first and second dielectric films overlying the lower portion of the first and second silicide layers, respectively, have a thickness of from about 2 to about 7 nanometers.

An integrated circuit comprising:

• a semiconductor substrate;
• a first fin and a second fin adjacent to each other extending from the semiconductor substrate, wherein the first fin has a first upper section and the second fin has a second upper section;
• a first epi-portion overlying the first upper section and a second epi-portion overlying the second upper section, wherein the first and second epi-portions are spaced apart from each other;
• a first silicide layer overlying the first epi-portion and a second silicide layer overlying the second epi-portion, wherein the first and second silicide layers are spaced apart from each other to define a lateral gap, and wherein first and second silicide layers comprise lower portions of the silicide layers;
• a dielectric spacer formed of a dielectric material and spanning the lateral gap above a void that is disposed between the first and second fins;
• lower dielectric film sections overlying the lower portions of the silicide layers, wherein the lower dielectric film sections have a thickness of from about 2 to about 7 nanometers, and wherein the void is disposed between the lower dielectric film sections;
• and
• a contact-forming material overlying the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer, wherein the dielectric material comprises SiN doped with C, N, O, or combinations thereof.