Passivated III-V or Ge fin-shaped field effect transistor

A method for manufacturing a semiconductor device, comprising the steps of:

• providing a structure having:
• a semiconductor substrate,
• a layer of a first dielectric material overlaying the substrate and defining at least one trench of depth h extending down to the substrate, and
• a filling including one or more layers selected from the group consisting of III-V compound layers and a Ge layer, the filling disposed in the at least one trench and forming a fin of height h within each of the at least one trench, thereby providing at least one fin, the at least one fin having side walls and a top surface;
• removing the layer of the first dielectric material in order to define at least one fin core structure having free side walls and a free top surface, and a recess exposing a substrate surface area around the at least one fin core structure;
• overlaying a coating onto the at least one fin core structure, thereby providing at least one coated fin having all side walls and the top surface coated with the coating, wherein the coating includes one or more metal oxide layers, at least one of which is aluminium;
• and
• filling in the recess so as to cover the exposed substrate surface area and the side walls of the at least one coated fin up to a certain height h′, which is less than the height h, with a second dielectric material.