Silicon-containing, tunneling field-effect transistor including III-N source
AssigneeInternational Business Machines Corporation
InventorsAnirban Basu, Bahman Hekmatshoartabari, Davood Shahrjerdi
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Abstract
Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A broken-band heterojunction is formed by the source and channel regions of the transistors. Fabrication methods include selective anisotropic wet-etching of a silicon substrate followed by epitaxial deposition of III-N material and/or germanium implantation of the substrate followed by the epitaxial deposition of the III-N material.
Claims14
A tunneling field-effect transistor comprising:
- a source region comprised of an epitaxial n-type III-N material including InGaN;
- a p-type drain region;
- a p-type SixGe1−x channel region operatively associated with the source and drain regions and forming a broken-band heterojunction with the source region, wherein x is between 0 and 1 and the n-type, III-N material has an electron affinity larger than the hole affinity of the channel region;
- a crystalline SixGe1−x substrate where x is greater than 0 and less than 1, the channel region being comprised of a portion of the crystalline SixGe1−x substrate, the source region comprising an epitaxial layer adjoining a (111) surface of the crystalline SixGe1−x substrate;
- a gate electrode, and
- a gate dielectric layer between the gate electrode and the channel region, the gate dielectric layer overlapping the source region.
A method of fabricating a tunneling field-effect transistor comprising:
- obtaining a crystalline SixGe1−x substrate, wherein x is equal to 1, the substrate having a top surface and a mask adjoining the top surface;
- patterning the mask to form one or more openings within the mask;
- anisotropically etching one or more recesses within the top surface of the substrate and aligned with the openings in the mask;
- epitaxially growing a III-N source region having n-type conductivity on the substrate and within the one or more recesses;
- removing the mask;
- implanting the substrate with germanium prior to growing the III-N source region;
- forming a channel region having p-type conductivity from the substrate, a broken-band heterojunction being formed between the source region and the channel region;
- forming a drain region having p-type conductivity operatively associated with the channel region;
- forming a gate dielectric layer on the substrate and adjoining the channel region, and
- forming a gate electrode over the gate dielectric layer.
Dependencies are inferred from the claim text.