US 9,425,311 B2Granted

MOS transistors and fabrication methods thereof

AssigneeSemiconductor Manufacturing International (Shanghai) Corporation

InventorsQingsong Wei, Shukun Yu

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Abstract

A method is provided for fabricating MOS transistors. The method includes providing a semiconductor substrate having at least a first region and a second region; and forming first transistors on the semiconductor substrate. Wherein source/drain regions of the first transistors are configured as SiGe growth regions; and a first density of SiGe growth regions in the first region is smaller than a second density of SiGe growth regions in the second region. The method also includes forming dummy SiGe growth regions in the first region to increase the first density such that the total density of SiGe growth regions in the first region is in a range similar to the second density; and forming trenches in the first region and the second region and the dummy SiGe growth region. Further, the method includes forming embedded source/drain regions of the first transistors and dummy SiGe regions.

Claims16

Dependent claims

A method for fabricating MOS transistors, comprising:

providing a semiconductor substrate having at least a first region and a second region;
forming PMOS transistors on the semiconductor substrate in the first region and the second region, wherein source/drain regions of the PMOS transistors are configured as SiGe growth regions;
and a first density of the SiGe growth regions in the first region is smaller than a second density of the SiGe growth regions in the second region;
after forming the PMOS transistors in the first region and the second region, separately forming dummy SiGe growth regions of dummy PMOS transistors in the first region to increase the first density, such that a total density of the SiGe growth regions from both the PMOS transistors and the dummy PMOS transistors in the first region equals to the second density of the SiGe growth regions from the PMOS transistors in the second region;
forming trenches by etching the SiGe growth regions in the first region and the second region and the dummy SiGe growth regions in the first region;
and
forming embedded source/drain regions of the PMOS transistors and dummy SiGe regions by forming SiGe in the trenches.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/279,469Filed 16 May 2014
Priority: CN 2013 1 019031221 May 2013
Published: US 2014/0346565 A127 Nov 2014
Granted: 23 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling
H10D 62/822
Heterojunctions: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
H10D 84/017
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their source or drain regions, e.g. silicided source or drain regions