Sidewall passivation for HEMT devices

An enhancement mode high electron mobility transistor (HEMT) formed on a substrate, comprising:

• an AlN buffer layer over the substrate;
• an AlGaN buffer layer over the AlN buffer layer;
• a GaN channel layer over the AlGaN buffer layer;
• an AlGaN barrier layer over the GaN channel layer, wherein source and drain regions directly contact an upper planar surface of the AlGaN barrier layer;
• a GaN gate structure in direct contact with the upper planar surface of the AlGaN barrier layer, wherein the GaN gate structure is doped with acceptor or donor impurities and has a gate structure upper surface and gate structure outer sidewalls;
• an AlN or BN conformal passivation layer in direct contact with the AlGaN barrier layer and extending over the gate structure upper surface and abutting the gate structure outer sidewalls;
• and
• a second passivation layer disposed conformally along outer sidewalls of the AlN or BN conformal passivation layer and over an upper surface of the AlN or BN conformal passivation layer, wherein the second passivation layer has a thickness of 50 nm to 500 nm, wherein a material composition of the second passivation layer is different from a material composition of the AlN or BN conformal passivation layer.

A high electron mobility transistor (HEMT), comprising:

• a heterojunction structure arranged over a semiconductor substrate, the heterojunction structure comprising:
• a channel layer comprising a first III-nitride material, and a barrier layer comprising a second III-nitride material;
• source and drain regions in direct contact with an upper surface of the heterojunction structure and spaced apart laterally from one another;
• a gate structure arranged over the heterojunction structure and arranged between the source and drain regions, wherein the gate structure comprises the first III-nitride material in direct contact with the upper surface of the heterojunction structure;
• a first passivation layer conformally disposed about sidewalls and an upper surface of the gate structure, and comprising a fourth III-nitride material;
• and
• a second passivation layer conformally disposed over the first passivation layer;
• wherein the first passivation layer has a first thickness and the second passivation layer has a second thickness that is greater than the first thickness.