Semiconductor devices
AssigneeSamsung Electronics Co., Ltd.
InventorMin-Hee Cho
Life of this patent
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Abstract
Semiconductor devices include an intrinsic semiconductor region on a substrate, a source region adjacent to a first side surface of the semiconductor region and doped with a p-type dopant, a drain region adjacent to a second side surface of the semiconductor region, a gate electrode on the semiconductor region, a source gate electrode on the source region, and a drain gate electrode on the drain region. The second side surface is a reverse side of the first side surface. The drain region is doped with a p-type dopant.
Claims20
A semiconductor device, comprising:
- an intrinsic semiconductor region on a substrate;
- a source region adjacent to a first side surface of the intrinsic semiconductor region, the source region being doped with a p-type dopant;
- a drain region adjacent to a second side surface of the intrinsic semiconductor region, the second side being a reverse side of the first side surface, and the drain region being doped with a p-type dopant;
- a gate electrode on the intrinsic semiconductor region;
- a source gate electrode on the source region;
- a drain gate electrode on the drain region;
- and
- a gate insulating layer interposed between the source gate electrode and the source region and between the drain gate electrode and the drain region.
A semiconductor device, comprising:
- a semiconductor layer on a substrate, the semiconductor layer extending in a first direction;
- a plurality of gate electrodes covering top and side surfaces of the semiconductor layer, the plurality of gate electrodes extending in a second direction perpendicular to the first direction;
- and
- a gate insulating layer interposed between the plurality of gate electrodes and the semiconductor layer,
- the semiconductor layer including an intrinsic semiconductor region, a source region formed adjacent to a first side surface of the intrinsic semiconductor region, and a drain region formed adjacent to a second side surface of the intrinsic semiconductor region,
- the source region and the drain region being doped with impurities of the same polarity, and
- the gate insulating layer being interposed between the plurality of gate electrodes and the source region and between the plurality of gate electrodes and the drain region.
A semiconductor device, comprising:
- a semiconductor layer consisting of a first semiconductor region interposed between a second semiconductor region and a third semiconductor region,
- the first semiconductor region being an undoped semiconductor region or an i-type semiconductor region, and
- the second and third semiconductor regions each being formed of a material having a smaller work function than a material forming the first semiconductor region;
- a metal pattern insulated from the semiconductor layer, the metal pattern including a plurality of gate electrodes over a respective one of the first, second and third semiconductor regions;
- and
- a gate insulating layer interposed between the plurality of gate electrodes and the semiconductor layer, the gate insulating layer being interposed between the plurality of gate electrodes and the second region and between the plurality of gate electrodes and the third region.
Dependencies are inferred from the claim text.