Stacked nanowires with multi-threshold voltage solution for pFETs
AssigneeInternational Business Machines Corporation
InventorsKarthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Abstract
A threshold voltage tuning approach for forming a stacked nanowire gate-all around pFET is provided. In the present application, selective condensation (i.e., oxidation) is used to provide a threshold voltage shift in silicon germanium alloy nanowires. The threshold voltage shift is well controlled because both underlying parameters which govern the final germanium content, i.e., nanowire width and amount of condensation, are well controlled by the selective condensation process. The present application can address the problem of width quantization in stacked nanowire FETs by offering various device options.
Claims10
A method of forming a semiconductor structure, said method comprising:
- providing a fin structure comprising, from bottom to top, a silicon portion and a multilayered stack of heterostructure portions, each heterostructure portion including, from bottom to top, a silicon germanium alloy portion having a first germanium content and a silicon portion, wherein each silicon germanium alloy portion of each heterostructure portion has a different thickness that increases from the bottommost heterostructure portion to the topmost heterostructure portion;
- suspending a middle segment of each silicon germanium alloy portion of each heterostructure portion;
- forming an oxygen impermeable structure atop the silicon germanium alloy portion of the topmost heterostructure portion and within a gap located beneath each silicon germanium alloy portion;
- recessing the oxygen impermeable structure below the silicon germanium alloy portion of the topmost heterostructure portion, while maintaining said oxygen impermeable structure on remaining silicon germanium alloy portions;
- oxidizing said silicon germanium alloy portion of the topmost heterostructure portion to provide a topmost silicon germanium alloy nanowire having a reduced thickness and a second germanium content that is greater than the first germanium content;
- removing surface oxide formed on said topmost silicon germanium alloy nanowire having said second germanium content;
- and
- repeating, any number of times, said steps of recessing said oxygen impermeable structure, said oxidizing, and said removing said surface on each remaining silicon germanium alloy portion of each heterostructure portion that is located above a bottommost silicon germanium alloy layer of the bottommost heterostructure portion to provide a nanowire stack containing silicon germanium alloy nanowires, wherein the germanium content of each silicon germanium alloy nanowire of said nanowire stack increases from bottom to top.
Dependencies are inferred from the claim text.