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US 9,425,283 B2Granted
Semiconductor device and method for manufacturing the same
AssigneeSK hynix Inc.
InventorsSuk Ki Kim, Kang Sik Choi
Life of this patent
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Abstract
A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance.
Claims8
A method for manufacturing a semiconductor device, the method comprising:
- forming a plurality of pillars on a semiconductor substrate;
- forming a gate electrode to surround each of the pillars;
- forming masking layer including a groove on the gate electrode and each of the pillars, wherein a top portion and an upper sidewall of each of the pillars are exposed by the groove;
- forming a silicide layer on the exposed top portion and the exposed upper sidewall of each of the pillars with maintaining an insulation between the silicide layer and the gate electrode;
- and
- forming a lower electrode on a whole surface of the silicide layer to fill the groove with a conductive material.
3 more elements
A method for manufacturing a semiconductor device, the method comprising:
- forming a pillar on a semiconductor substrate;
- forming a gate insulating layer on the pillar and the semiconductor substrate;
- forming a gate material on the semiconductor substrate;
- recessing the gate material so that a remained gate material includes a height being lower than that of the pillar;
- forming a first spacer to surround a circumference of the pillar, on the remained gate material;
- forming a second spacer to surround a circumference of the first spacer;
- patterning the gate material using the first and the second spacers as a mask, to form a gate electrode;
- exposing a top portion of the pillar and an upper sidewall extending from an edge of the top portion of the pillar by removing a portion of the first spacer;
- forming a silicide layer on the exposed top portion and the exposed upper sidewall of the pillar with maintaining an insulation between the silicide layer which is formed at the upper sidewall of each of the pillars and the gate electrode;
- and
- forming a lower electrode on a whole surface of the silicide layer.
8 more elements
Dependencies are inferred from the claim text.