Semiconductor integrated circuit device having vertical channel and method of manufacturing the same
AssigneeSK hynix Inc.
InventorKang Sik Choi
Life of this patent
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Abstract
A semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same are provided. A plurality of active lines are formed in a semiconductor substrate. A gate electrode having a lower height than each active line is formed on a sidewall of the active line. A first insulating layer having a height lower than that of the active line and higher than that of the gate electrode is buried between active lines, and a silicide layer is formed on an exposed upper surface and a lateral surface of the active line.
Claims10
A method of manufacturing a semiconductor integrated circuit device, the method comprising:
- forming an active line over a semiconductor substrate, the active line including a first sidewall and a second sidewall;
- forming a first gate electrode over a lower portion of the first sidewall of the active line;
- forming a second gate electrode over a lower portion of the second sidewall of the active line;
- forming a first insulating layer between the active line and a neighboring active line to bury the first and the second gate electrodes, wherein an upper portion of the active line is exposed over the first insulating layer;
- forming a drain region in the upper portion of the active line and forming a common source region extending from the semiconductor substrate under the active line to the semiconductor substrate under the neighboring active line;
- and
- forming a silicide layer over an upper surface and a sidewall of the upper portion of the active line,
- wherein the first and the second gate electrodes are formed to be parallel with the active line.
A method of manufacturing a semiconductor integrated circuit device, the method comprising:
- forming first and second active lines, extending parallel to each other, over a semiconductor substrate, wherein each of the active lines has a first conductivity type;
- forming a gate electrode over a lower sidewall of the first active line, wherein the gate electrode has a linear shape;
- gap-filling a first insulating layer between the first and the second active lines, wherein the first insulating layer extends up to a level higher than the gate electrode;
- forming a drain region in an upper portion of the first active line and forming a source region in the semiconductor substrate under the first active line, wherein each of the drain and the source regions has an impurity having a second conductivity type opposite to the first conductivity type, wherein the upper portion of the first active line is exposed over the gate electrode;
- forming a silicide layer extending from an upper surface of the drain region to a sidewall of the drain region;
- gap-filling a second insulating layer over the silicide layer and over the first insulating layer;
- and
- etching the first active line using a mask extending in a direction substantially perpendicular to the first active line to form an active pillar,
- wherein an upper portion of the active pillar is covered by the silicide layer.
Dependencies are inferred from the claim text.