US 9,425,280 B2Granted

Semiconductor device with low-K spacers

AssigneeGlobalfoundries Inc.

InventorsXiuyu Cai, Ruilong Xie, Xunyuan Zhang

Life of this patent

Estimating the term…

Loading patent…

Abstract

One method disclosed herein includes forming at least one sacrificial sidewall spacer adjacent a sacrificial gate structure that is formed above a semiconducting substrate, removing at least a portion of the sacrificial gate structure to thereby define a gate cavity that is laterally defined by the sacrificial spacer, forming a replacement gate structure in the gate cavity, removing the sacrificial spacer to thereby define a spacer cavity adjacent the replacement gate structure, and forming a low-k spacer in the spacer cavity. A novel device disclosed herein includes a gate structure positioned above a semiconducting substrate, wherein the gate insulation layer has two upstanding portions that are substantially vertically oriented relative to an upper surface of the substrate. The device further includes a low-k sidewall spacer positioned adjacent each of the vertically oriented upstanding portions of the gate insulation layer.

Claims17

Dependent claims

A device, comprising:

a gate structure positioned above an active region defined in a semiconducting substrate, said gate structure comprising a gate insulation layer and a gate electrode, said gate insulation layer having two upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate;
a first layer of insulating material positioned above and covering at least a portion of said active region;
a second layer of insulating material positioned above and covering at least a portion of said first layer of insulating material;
a third layer of insulating material positioned above and covering at least a portion of said second layer of insulating material;
and
a low-k sidewall spacer positioned adjacent each of said vertically oriented upstanding portions of said gate insulation layer, wherein said low-k sidewall spacer contacts each of said first, second, and third layers of insulating material, wherein a portion of said low-k sidewall spacer extends into a recess that is positioned between said third layer of insulating material and said active region, said portion of said low-k sidewall spacer contacting a sidewall portion of said second layer of insulating material.

3 more elements

A device, comprising:

a gate structure positioned above an active region defined in a semiconducting substrate, said gate structure comprising a gate insulation layer comprised of a high-k insulating material and a gate electrode comprised of at least one layer of metal, said gate insulation layer having two upstanding portions that are substantially vertically oriented relative to an upper surface of said substrate;
a low-k sidewall spacer that is positioned adjacent to and contacts each of said vertically oriented upstanding portions of said gate insulation layer, wherein said low-k sidewall spacer is comprised of a material having a k value of less than 7;
a void positioned within said low-k sidewall spacer;
a first layer of insulating material positioned above said semiconducting substrate and covering at least a portion of an upper surface of said active region;
a second layer of insulating material positioned above said semiconducting substrate and covering at least a portion of an upper surface of said first layer of insulating material;
a third layer of insulating material positioned above and covering at least a portion of an upper surface of said second layer of insulating material;
and
a fourth layer of insulating material positioned above and covering at least a portion of an upper surface of said third layer of insulating material, wherein said low-k sidewall spacer contacts an upper surface of said first layer of insulating material and a sidewall surface of each of said second, third, and fourth layers of insulating material.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/711,196Filed 13 May 2015 · division
Priority: 22 Oct 2012
Published: US 2015/0255561 A110 Sep 2015
Granted: 23 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 64/679
Gate sidewall spacers: comprising air gaps
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
H10D 62/021
Manufacture or treatment: forming source or drain recesses by etching e.g. recessing by etching and then refilling
H10D 64/015
Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers

Family

Application13/656,794Parent of this division · filed 22 Oct 2012
US 2015/0255561 A1Pre-grant publication · published 10 Sep 2015
US 9,064,948 B2Parent of this division
US 2014/0110798 A1Published application
US 9,425,280 B2This patent

From the US filing history. Foreign family members aren’t listed.