Segregated FinFET structure and manufacturing method
AssigneeSemiconductor Manufacturing International (Shanghai) Corporation
InventorFumitake Mieno
Life of this patent
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Abstract
A semiconductor device includes a semiconductor fin on a substrate. The semiconductor fin includes a stack of alternating layers of first and second materials that induce stress or strain to the channel of the semiconductor device for implementing a strained FinFET. The first and second materials are different. The second material layers include lateral recesses filled with an insulating layer to form an isolated FinFET structure to further induce stress in the channel region to improve the performance of the semiconductor device.
Claims15
A method of manufacturing a semiconductor device comprising:
- providing a substrate;
- forming a semiconductor fin having a laminated structure on the substrate, the laminated structure having a stack of alternating first material layers and second material layers;
- forming a shallow trench insulation structure on opposite sides of the semiconductor fin;
- selectively removing portions of the second material layers to obtain lateral recesses with respect to the first material layers;
- and
- forming an insulating layer filling the lateral recesses and directly on an upper surface and side surfaces of the semiconductor fin protruding over a surface of the shallow trench insulation structure as a gate insulation layer, wherein the insulating layer filling the lateral recesses has a thickness greater than a thickness of the gate insulating layer.
A semiconductor device comprising:
- a substrate;
- a semiconductor fin on the substrate, the semiconductor fin having a stack of alternating first material layers and second material layers, the second material layers comprising lateral recesses with respect to the first material layers;
- a shallow trench insulating structure disposed on opposite sides of the semiconductor fin;
- and
- an insulating layer filling the lateral recesses and directly on an upper surface and side surfaces of the semiconductor fin protruding over a surface of the shallow trench insulation structure as a gate insulation layer, wherein the insulating layer filling the lateral recesses has a thickness greater than a thickness of the gate insulating layer.
Dependencies are inferred from the claim text.