Integrated circuit chips having field effect transistors with different gate designs
AssigneeSamsung Electronics Co., Ltd.
InventorsMark S. Rodder, Dharmendar Reddy Palle, Borna J. Obradovic
Life of this patent
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Abstract
An integrated circuit chip includes a semiconductor substrate, a first back-end-of-line unit circuit that includes a first group of field effect transistors, a second gate-loaded unit circuit that includes a second group of field effect transistors. The first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor. A bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor.
Claims20
An integrated circuit chip, comprising:
- a semiconductor substrate;
- a first back-end-of-line-loaded unit circuit that includes a first group of field effect transistors;
- and
- a second gate-loaded unit circuit that includes a second group of field effect transistors;
- wherein the first group of field effect transistors includes a first transistor and the second group of field effect transistors includes a second transistor, and
- wherein a bottom surface of a gate electrode of the first transistor extends closer to a bottom surface of the semiconductor substrate than does a bottom surface of a gate electrode of the second transistor.
An integrated circuit chip, comprising:
- a semiconductor substrate;
- a first unit circuit that includes first unit cells having a first plurality of field effect transistors on the semiconductor substrate and a first plurality of interconnects that interconnect the first plurality of field effect transistors;
- a second unit circuit that includes second unit cells having a second plurality of field effect transistors on the semiconductor substrate and a second plurality of interconnects that interconnect the second plurality of field effect transistors;
- wherein a first transistor that is part of the first plurality of field effect transistors has a first gate design, and wherein more than 50% of the circuit capacitance of the first unit circuit is attributable to the first plurality of interconnects, and
- wherein a second transistor that is part of the second plurality of field effect transistors has a second gate design that is different from the first gate design, and wherein less than 50% of the circuit capacitance of the second unit circuit is attributable to the second plurality of interconnects.
An integrated circuit chip, comprising:
- a first unit circuit that has first field effect transistors that have respective gate capacitance levels that sum to a value that exceeds a first threshold, the first field effect transistors having a first gate electrode design;
- and
- a second unit circuit that has second field effect transistors that have respective gate capacitance levels that sum to a second value that is less than a second threshold, the second field effect transistors having a second gate electrode design that is different than the first gate electrode design.
Dependencies are inferred from the claim text.