Transistor with charge enhanced field plate structure and method

A transistor device, comprising:

• a substrate;
• a passivation surface layer covering the substrate with a gate electrode opening formed therein;
• a conductive gate electrode located in the gate electrode opening to be in contact with the substrate;
• a first dielectric layer over the conductive gate electrode;
• a charged dielectric layer over at least a portion of the first dielectric layer and overlapping at least a portion of the conductive gate electrode, the charged dielectric layer formed to include open bonds to provide a fixed sheet charge density of at least 5E1013 cm−2;
• and
• a field plate overlapping at least a portion of the charged dielectric layer.

A transistor device, comprising:

• a substrate;
• a passivation surface layer covering the substrate with a gate electrode opening formed therein;
• a conductive gate electrode located in the gate electrode opening to be in contact with the substrate;
• a first dielectric layer over the conductive gate electrode;
• a charged dielectric layer over at least a portion of the first dielectric layer and overlapping at least a portion of the conductive gate electrode, the charged dielectric layer formed in a non-stoichiometric manner to include open bonds to provide a fixed charge density in the charged dielectric layer;
• a field plate overlapping at least a portion of the charged dielectric layer;
• and
• a circuit, the circuit coupled to the field plate, the circuit configured to drive the field plate to cause the field plate to inject charge into the charged dielectric layer until the charged dielectric layer has a fixed sheet charge density of at least 5E1013 cm−2, and wherein the circuit is further configured to selectively modulate the charge in the charged dielectric layer to cause an adjustment of capacitances between the field plate and the gate electrode and between the gate electrode and the drain electrode.