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US 9,425,255 B2Granted
Nanowire and planar transistors co-integrated on utbox SOI substrate
AssigneesCommissariat A L'energie Atomique Et Aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
InventorsSylvain Barraud, Yves Morand
Life of this patent
Estimating the term…
Abstract
Fabrication of a microelectronic device on a semiconductor on insulator type substrate, the device being provided with a transistor of a given type, the channel structure of which is formed from semiconducting bar(s), a dielectric area different from the insulating layer of the substrate being provided to replace the insulating layer, facing the transistor channel structure, specifically for this given type of transistor.
Claims5
A microelectronic device comprising:
- a substrate comprising a thin semiconducting layer supported on an insulating layer, said insulating layer being supported on a semiconducting support layer,
- at least one first transistor of a first type comprising a region suitable for forming a channel, the region comprising one or several adjacent bars, arranged in and/or on said thin semiconducting layer and an encasing gate arranged on said bars and around side faces of said bars, said channel of said first transistor being arranged on an area based on a given dielectric material different from that of said insulating layer,
- the composition and thickness of said given dielectric material facilitating capacitive coupling between said channel of said first transistor and said semiconducting support layer of said substrate and/or said given dielectric material with a dielectric constant k2 such that k2>k1, where k1 is the dielectric constant of the insulating layer material.
Dependencies are inferred from the claim text.