Vertical transistor for resistive memory
AssigneeSTMicroelectronics (Rousset) SAS
InventorsPhilippe Boivin, Julien Delalleau
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to a memory on semiconductor substrate, comprising: at least one data line, at least one selection line, at least one reference line, at least one memory cell comprising a select transistor having a control gate connected to the selection line, a first conduction terminal connected to a variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, the select transistor comprising an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, between a first deep doped region and a second doped region on the surface of the substrate coupled to the variable impedance element.
Claims18
A memory on a semiconductor substrate, comprising:
- a data line,
- a selection line,
- a reference line,
- a memory cell that includes a variable impedance element and a select transistor having a control gate electrically coupled to the selection line, a first conduction terminal electrically coupled to the variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, wherein:
- the select transistor comprises a deep first doped region buried in the substrate,
- the first conduction terminal is a second doped region on a surface of the substrate and electrically coupled to the variable impedance element,
- the control gate is an embedded vertical gate produced in a trench formed in the substrate, and
- the select transistor includes a channel region opposite a first face of the trench and extending between the first doped region and the second doped region.
A memory cell, comprising:
- a variable impedance element;
- and
- a select transistor having a first conduction terminal electrically coupled to the variable impedance element, a deep first doped region buried in a substrate, an embedded vertical gate produced in a trench formed in the substrate, and a channel region opposite a first face of the trench, the first conduction terminal being a second doped region adjacent to an upper surface of the substrate and the channel region extending between the first doped region and the second doped region.
A memory, comprising:
- a semiconductor substrate;
- a data line,
- a selection line,
- a reference line,
- a memory cell that includes a variable impedance element and a select transistor having a control gate electrically coupled to the selection line, a first conduction terminal electrically coupled to the variable impedance element, the select transistor and the variable impedance element coupling the reference line to the data line, wherein:
- the select transistor comprises a deep first doped region buried in the substrate,
- the first conduction terminal is a second doped region at an upper surface of the substrate and electrically coupled to the variable impedance element,
- the control gate is an embedded vertical gate produced in a trench formed in the substrate,
- the select transistor includes a channel region opposite a first face of the trench and extending between the first doped region and the second doped region, and
- an insulating layer is positioned on the upper surface of the substrate and the variable impedance layer is positioned in the insulating layer.
Dependencies are inferred from the claim text.