Manufacture method of TFT substrate and sturcture thereof

A manufacture method of a TFT substrate, comprising steps of:

• step 1, providing a substrate and deposing a first metal layer on the substrate;
• step 2, coating a first photoresistor layer on the first metal layer, and implementing gray scal exposure to the first photoresistor layer by a first mask process for patterning the first photoresistor layer to form a first photoresistor area, a second photoresistor area and a third photoresistor area spaced with one another;
• step 3, removing the first metal layer uncovered by the first, the second and the third photoresistor areas to form a gate and a source/a drain;
• step 4, implementing ashing process to the first, the second and the third photoresistor areas to reserve a part of the first photoresistor area, a part of the second photoresistor area;
• removing the third photoresistor area;
• the part of the first photoresistor area and the part of the second photoresistor area respectively correspond to a first, a second and a third vias of an isolation layer to be formed;
• step 5, deposing the isolation layer on the substrate, the gate, the source/the drain, the part of the first photoresistor area and the part of the second photoresistor area;
• step 6, removing the part of the first photoresistor area, the part of the second photoresistor area and the isolation layer deposed on the both to form the first, the second and the third vias for exposing the gate and the source/the drain;
• step 7, deposing an oxide semiconductor thin film on the isolation layer, and a second mask to implement a photolithography process, and implementing etching, patterning and anneal processes to the oxide semiconductor thin film to form an oxide semiconductor layer;
• the oxide semiconductor layer partially fills the first, the second vias, and contacts the source/the drain to form electrical connections;
• step 8, deposing a protecting layer on the oxide semiconductor layer and the isolation layer;
• step 9, coating a second photoresistor layer on the protecting layer, and implementing gray scal exposure to the second photoresistor layer by a third mask process for patterning the second photoresistor layer to form a fourth photoresistor area, a fifth photoresistor area, a sixth photoresistor area and a seventh photoresistor area spaced with one another;
• step 10, removing the protecting layer uncovered by the fourth photoresistor area, the fifth photoresistor area, the sixth photoresistor area and the seventh photoresistor area to form a first, a second and a third through holes for exposing the gate and the source/the drain;
• step 11, implementing ashing process to the second photoresistor layer to reserve a part of the fourth photoresistor area and a part of the fifth fourth photoresistor area;
• removing the sixth photoresistor area and the seventh photoresistor area;
• step 12, deposing a transparent conducting thin film on the part of the fourth photoresistor area, the part of the fifth fourth photoresistor area, the protecting layer, the gate, the source/the drain, and a part of the transparent conducting thin film is employed as a landing electrode to fill the second and the third through holes for connecting the gate and the source/the drain, and a part of the transparent conducting thin film is employed as a pixel electrode to fill the first through hole and connect the source/the drain;
• step 13, removing the part of the fourth photoresistor area, the part of the fifth fourth photoresistor area and the transparent conducting thin film deposed on the both, and implementing anneal process;
• step 14, coating photoresistor on the transparent conducting thin film and the protecting layer, and implementing exposure and development by a fourth mask to define illuminating display positions and form a pixel definition layer;
• step 15, coating photoresistor on the pixel definition layer, and implementing exposure and development by a fifth mask to form photo spacers.