Semiconductor memory device and method for manufacturing same
AssigneeKabushiki Kaisha Toshiba
InventorToshiyuki Sasaki
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Abstract
According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.
Claims20
A semiconductor device comprising:
- first memory cells provided in a first stacked body including first electrode layers alternately stacked with a plurality of insulating layers therebetween, the first memory cells having the first electrode layers as control gates and a first semiconductor portion as channels extending inside the first stacked body;
- second memory cells provided in a second stacked body including second electrode layers alternately stacked with a plurality of insulating layers therebetween, the second memory cells having the second electrode layers as control gates and a second semiconductor portion as channels extending inside the second stacked body;
- and
- an interlayer cell having a conductive layer provided above the first stacked body and below the second stacked body and a third semiconductor portion provided between the first semiconductor portion and the second semiconductor portion, the interlayer cell and the first and second memory cells being connected in series via the first to third semiconductor portions, wherein
- the interlayer cell is not used for storing data.
A semiconductor memory device comprising:
- a source-side selection gate;
- first electrode layers provided above the source-side selection gate via a first insulating layer, the first electrode layers being alternately stacked with a plurality of insulating layers therebetween;
- second electrode layers provided above the first electrode layers via an inter-electrode insulating layer, the second electrode layers being alternately stacked with a plurality of insulating layers therebetween;
- a drain-side selection gate provided above the second electrode layers via a second insulating layer;
- and
- an intermediate layer capable of being applied with a potential provided between the first electrode layers and the second electrode layers, wherein
- the source-side selection gate controls a source-side selection transistor, the drain-side selection gate controls a drain-side selection transistor, the first electrode layers and the second electrode layers respectively control first memory cells and second memory cells both capable of storing data, and the intermediate layer controls a cell not used for storing data;
- and
- the source-side selection transistor, the first memory cells, the cell not used for storing data, the second memory cells, and the drain-side selection transistor are connected in series via a semiconductor channel.
Dependencies are inferred from the claim text.