Multilayer 3-D structure with mirror image landing regions

A 3-D structure comprising:

• a substrate;
• first and second units of alternating levels of insulating layers and active layers over the substrate;
• the first unit comprising active layers 1 through n with active layer 1 of the first unit being at a chosen level;
• the second unit comprising active layers 1 through n with active layer 1 of the second unit being at said chosen level;
• each of the first and second units including a stair step arrangement of landing regions on active layers;
• the landing regions of the first and second units being mirror image surfaces of one another;
• an insulating layer over the landing regions;
• and
• interlayer conductors passing through the insulating layer to the stairstep arrangements of landing regions for the first and second units to make electrical contact with a plurality of landing regions of each unit.

A 3-D structure comprising:

• a substrate;
• first and second units of alternating levels of insulating layers and active layers over the substrate;
• the first unit comprising active layers 1 through n with active layer 1 of the first unit being at a chosen level, n being a positive integer greater than 3;
• the second unit comprising active layers 1 through m with active layer 1 of the second unit being at said chosen level, m being a positive integer less than or equal to n;
• each of the first and second units including a stair step arrangement of landing regions on active layers and side surfaces extending from the landing regions;
• the landing regions and the side surfaces of the first and second units being mirror image surfaces of one another for active layers 1-m;
• an etch stop layer over the landing regions and side surfaces of the first and second units creating etch stop sidewalls along the side surfaces;
• an insulating layer over the etch stop layer;
• a plurality of blocks, blocks in the plurality of blocks comprising a plurality of levels L(z) corresponding to active layers 1 through n, levels L(z) in the plurality of levels including respective two dimensional arrays of memory cells, respective two dimensional arrays including a plurality of horizontal lines, the plurality of horizontal lines being a chosen one of bit lines or word lines, and being intersected by a plurality of vertical lines coupled to corresponding memory cells in the array, the plurality of vertical lines being the non-chosen one of the bit lines or word lines, wherein levels in the plurality of levels are connected to said landing regions of the corresponding active layers so that the landing regions are in electrical communication with the plurality of horizontal lines for a given block;
• and
• interlayer conductors passing through the insulating layer and the etch stop layer to the stairstep arrangements of landing regions for the first and second units to make electrical contact with a plurality of landing regions of each unit.