Vertical memory devices
AssigneeSamsung Electronics Co., Ltd.
InventorsHong-Soo Kim, Sung-Hoi Hur, So-Wi Chin
Life of this patent
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Abstract
A vertical memory device includes a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure comprising a transistor, a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate, a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels, and a blocking structure between the cell region and the peripheral circuit region, wherein a height of the blocking structure is greater than a height of the gate structure in the peripheral region.
Claims20
A vertical memory device, comprising:
- a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure, the gate structure including a transistor;
- a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate;
- a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels;
- and
- a blocking structure between the cell region and the peripheral circuit region, a height of the blocking structure being greater than a height of the gate structure in the peripheral circuit region.
A vertical memory device, comprising:
- a substrate including a cell region and a peripheral circuit region, the peripheral circuit region including a gate structure, the gate structure including a transistor;
- a plurality of channels on the cell region, each of the channels extending in a first direction that is vertical with respect to a top surface of the substrate;
- a plurality of gate lines stacked in the first direction and spaced apart from each other, the gate lines surrounding outer sidewalls of the channels;
- a common source line on the cell region;
- and
- a blocking structure between the cell region and the peripheral circuit region, the blocking structure surrounding the cell region, a height of the blocking structure being greater than a height of the gate structure in the peripheral circuit region.
A vertical memory device, comprising:
- a substrate including a cell region, a blocking region and a peripheral circuit region, the peripheral circuit region including a gate structure, the gate structure including a transistor;
- a gate line structure on the cell region, the gate line structure including
- a plurality of insulating interlayer patterns and a plurality of gate lines alternately stacked in a first direction that is vertical with respect to a top surface of the substrate,
- a plurality of channels extending through the plurality of insulating interlayer patterns and the plurality of gate lines;
- a peripheral circuit on the peripheral circuit region;
- and
- a blocking structure on the blocking region, the blocking structure defining a boundary between the gate line structure and the peripheral circuit region, a height of the blocking structure being greater than a height of the gate structure in the peripheral circuit region.
Dependencies are inferred from the claim text.