US 9,425,207 B2Granted

Memory device with different memory film diameters in the same laminate level

AssigneeKabushiki Kaisha Toshiba

InventorNaoki Yasuda

Life of this patent

Estimating the term…

Loading patent…

Abstract

According to one embodiment, a non-volatile memory device includes first electrodes, at least one first semiconductor layer, a first memory film, second electrodes, at least one second semiconductor layer, and a second memory film. The first electrodes are stacked in a first direction. The one first semiconductor layer extends in the first direction through the first electrodes. The first memory film is provided between each of the first electrodes and the one first semiconductor layer. The second electrodes are stacked in the first direction and provided together with the first electrodes in a second direction orthogonal to the first direction. The one second semiconductor layer extends in the first direction through the second electrodes. The second memory film is provided between each of the second electrodes and the one second semiconductor layer. An outer diameter of the first memory film is larger than that of the second memory film.

Claims15

Dependent claims

A non-volatile memory device comprising:

a plurality of first electrodes stacked in a first direction;
at least one first semiconductor layer extending in the first direction through the first electrodes;
a first memory film provided between each of the first electrodes and the first semiconductor layer;
a plurality of second electrodes stacked in the first direction and provided together with the first electrodes in a second direction orthogonal to the first direction;
at least one second semiconductor layer extending in the first direction through the second electrodes;
and
a second memory film provided between each of the second electrodes and the second semiconductor layer,
an outer diameter of the first memory film provided between one of the first electrodes and the first semiconductor layer being larger than an outer diameter of the second memory film provided between one of the second electrodes positioned in the same laminate level as the one of the first electrodes and the second semiconductor layer.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/521,577Filed 23 Oct 2014 · us provisional application
Priority: 3 Jul 2014
Published: US 2016/0005755 A17 Jan 2016
Granted: 23 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10B 43/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
G11C 11/5671
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge trapping in…
G11C 16/14
Programming or data input circuits: circuits for erasing electrically, e.g. erase voltage switching circuits
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout