Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology

An integrated circuit (IC) comprising:

• a semiconductor substrate comprising an embedded memory region and a periphery region separated by a boundary region;
• a non-volatile memory (NVM) or a poly SiON (silicon oxy-nitride) CMOS device disposed over the embedded memory region;
• a periphery circuit disposed over the periphery region;
• an angled first dummy structure positioned at a first end of the embedded memory region;
• and
• a second dummy structure positioned at a second end of the periphery region.

A method of forming an integrated circuit (IC), comprising:

• providing a semiconductor substrate comprising a first region and a second region laterally separated from the first region by a boundary region;
• forming a non-volatile memory (NVM) device over the first region;
• forming one or more HKMG (high-k metal gate) CMOS devices over the second region;
• and
• forming a first dummy structure at a position laterally disposed between the NVM device and the one or more HKMG CMOS devices;
• forming a second dummy structure at a position laterally disposed between the first dummy structure and the HKMG CMOS devices.