US 9,425,202 B2Granted

Split page 3D memory array

AssigneeMacronix International Co., Ltd.

InventorGuan-Ru Lee

Life of this patent

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Abstract

A semiconductor device includes active strips. Active strip stack selection structures electrically couple to the active strip stacks at positions between the first and second ends, and select particular ones of the active strip stacks for operations. In one embodiment, different pads coupled to opposite pads have a higher voltage, depending on the memory cell selected for read. The same active strip stack selection structure can act as a pair of side gates for opposite sides of a first active strip stack, and as one side gate for each of the adjacent active strip stacks. Each active strip stack can have: a first structure from a first set acting as first and second side gates on a first side of word lines; and a second structure and a third structure from a second set respectively acting as third and fourth side gates on the second side of word lines.

Claims17

Dependent claims

An integrated circuit with a memory array, comprising:

a plurality of active strip stacks with memory cells of the memory array, active strip stacks in the plurality of active strip stacks having first ends and second ends;
and
a plurality of active strip stack selection structures electrically coupled to the plurality of active strip stacks at positions between the first ends and the second ends, the plurality of active strip stack selection structures selecting particular ones of the plurality of active strip stacks for operations, the plurality of active strip stack selection structures are double gate structures, the plurality of active strip stack selection structures including:
a first set of active strip stack selection structures on a first side of a plurality of word lines;
and
a second set of active strip stack selection structures on a second side of the plurality of word lines, and wherein a particular active strip stack of the plurality of active strip stacks has:
a first active strip stack selection structure from the first set of active strip stack selection structures acting as first and second side gates on said particular active strip stack on the first side of the plurality of word lines;
and
a second active strip stack selection structure and a third active strip stack selection structure from the second set of active strip stack selection structures respectively acting as third and fourth side gates on said particular active strip stack on the second side of the plurality of word lines.

6 more elements

An integrated circuit with a memory array, comprising:

a plurality of active strip stacks with memory cells of the memory array, active strip stacks in the plurality of active strip stacks having a stack width, and first ends and second ends, adjacent ones of the plurality of active strip stacks positioned apart by a gap width;
a plurality of active strip stack selection structures, active strip stack selection structures in the plurality of active strip stack selection structures electrically coupled to the plurality of active strip stacks at positions between the first ends and the second ends, the plurality of active strip stack selection structures select particular ones of the plurality of active strip stacks for operations, the plurality of active strip stack selection structures having a structure width greater than a sum of:
(i) the stack width and (ii) twice the gap width, and less than a sum of:
(i) twice the stack width and (ii) twice the gap width.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 14/670,105Filed 26 Mar 2015 · division
Priority: 24 Oct 2013
Published: US 2015/0117101 A116 Jul 2015
Granted: 23 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10B 69/00
Erasable-and-programmable rom [eprom] devices not provided for in groups h10b41/00 - h10b63/00
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 7/14
Arrangements for writing information into, or reading information out from, a digital store: dummy cell management; Sense reference voltage generators
G11C 16/04
Electrically programmable: using variable threshold transistors, e.g. FAMOS

Family

Application14/062,487Parent of this division · filed 24 Oct 2013
US 2015/0200195 A1Pre-grant publication · published 16 Jul 2015
US 9,019,768 B1Parent of this division
US 2015/0117101 A1Published application
US 9,425,202 B2This patent

From the US filing history. Foreign family members aren’t listed.