Cell layout for SRAM FinFET transistors
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon Jhy Liaw
Life of this patent
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Abstract
An SRAM array and method of making is disclosed. Each SRAM cell comprises two pull-up (PU), two pass-gate (PG), and two pull-down (PD) FinFETs. The PU transistors are adjacent to each other and include one active fin having a first fin width. Each PG transistor shares at least one active fin with a PD transistor. The active fin shared by a PG and a PD transistor has a second fin width smaller than the first fin width. The method includes patterning a plurality of fins including active fins and dummy fins and patterning and removing at least a portion of the dummy fins. No dummy fin is disposed between PU FinFETs in a memory cell. One dummy fin is disposed between a PU FinFET and the at least one active fin shared by a PG and a PD transistor. At least one dummy fin is disposed between adjacent memory cells.
Claims20
An SRAM cell array comprising:
- a plurality of SRAM cells, each SRAM cell comprising six FinFETs including two pull-up (PU) transistors, two pass-gate (PG) transistors, and two pull-down (PD) transistors;
- wherein each PU transistor includes one active fin having a first fin width, the one active fin of each PU transistor being adjacent to each other;
- wherein each PG transistor shares at least one active fin with a PD transistor;
- wherein the at least one active fin shared by a PG transistor and a PD transistor has a second fin width smaller than the first fin width;
- and
- wherein no dummy fin is disposed between the one active fin of each PU transistor in a memory cell, a dummy fin is disposed between a PU transistor and the at least one active fin shared by a PG transistor and the PD transistor, and at least one dummy fin is disposed between the at least one active fin shared by the PG transistor and PD transistor in the memory cell and a fin shared by a PG transistor and a PD transistor in an adjacent memory cells.
An SRAM cell array, each cell comprising:
- a first fin electrically coupled as a source/drain of a first pass-gate transistor and a source/drain of a first pull-down transistor;
- a second fin electrically coupled as a source/drain of a first pull-up transistor;
- a third fin electrically coupled as a source/drain of a second pull-up transistor;
- and
- a fourth fin electrically coupled as a source/drain of a second pass-gate transistor and a source/drain of a second pull-down transistor;
- wherein the second fin and the third fin are interposed between the first fin and the fourth fin;
- and
- wherein a first distance between the first fin and a closest fin of the second fin and the third fin is greater than a second distance between the second fin and the third fin.
An SRAM cell array, each cell comprising:
- a first pass-gate transistor and a first pull-down transistor sharing a first fin;
- a first pull-up transistor including a second fin;
- a second pull-up transistor including a third fin;
- and
- a second pass-gate transistor and a second pull-down transistor sharing a fourth fin;
- wherein the second fin and the third fin are interposed between the first fin and the fourth fin;
- wherein the first fin has a first ratio of a first fin top width to a first fin bottom width;
- wherein the second fin has a second ratio of a second fin top width to a second fin bottom width;
- and
- wherein the first ratio is greater than the second ratio.
Dependencies are inferred from the claim text.