Static discharge system
AssigneePower Integrations, Inc.
InventorsAlexey Kudymov, Jamal Ramdani
Life of this patent
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Abstract
A semiconductor circuit includes a three-terminal high voltage semiconductor device, a charge distribution structure and a static discharge system. The charge distribution structure has a plurality of conductors with a floating potential. The charge distribution structure is capacitively coupled to a first terminal of the semiconductor device. The static discharge system removes charge that accumulates on at least a subset of the conductors. The static discharge system removes the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state.
Claims24
A semiconductor circuit, comprising:
- a three-terminal high voltage semiconductor device;
- a charge distribution structure having a plurality of conductors with a floating potential, said charge distribution structure being capacitively coupled to a first terminal of the semiconductor device;
- and
- a static discharge system removing charge that accumulates on at least a subset of the conductors, said static discharge system removing the charge that accumulates on the subset of conductors when the semiconductor device is in a first state while allowing charge to accumulate on the subset of conductors when the semiconductor device is in a second state.
A semiconductor structure, comprising:
- a substrate having first and second active areas spatially separated from one another;
- a first active layer disposed on the first and second active areas of the substrate;
- a second active layer disposed on the first active layer such that a lateral conductive channel arises between the first active layer and the second active layer;
- a source, gate and drain contact disposed over a first portion of the second active layer located on the first active area of the substrate to define a HFET;
- a plurality of conductors disposed over the second active layer between the gate and drain contacts, a first of said conductors being capacitively coupled to the gate contact and a second of said conductors being capacitively coupled to the first conductor;
- and
- a series of contacts disposed over a second portion of the second active layer located on the second active area of the substrate to define a plurality of transistors such that one of the contacts is a junction contact that serves as a drain contact of a first of the transistors and a source contact of a second of the transistors, the plurality of transistors being electrically coupled to the HFET.
Dependencies are inferred from the claim text.