US 9,425,194 B2Granted

Transistor devices with high-k insulation layers

AssigneeGlobalfoundries Inc.

InventorsMartin Gerhardt, Stefan Flachowsky, Matthias Kessler

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Abstract

An integrated circuit product includes first and second transistors positioned in and above first and second active regions. The first transistor has a first gate length and a first gate material stack that includes a first gate dielectric layer having a first thickness and at least one layer of metal positioned above the first gate dielectric layer, the first gate dielectric layer including a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on the layer of the first high-k insulating material. The second transistor has a second gate length and a second gate material stack that includes a second gate dielectric layer having a second thickness positioned above the second active region and at least one layer of metal positioned above the second gate dielectric layer, the second gate dielectric layer including a layer of the second high-k insulating material.

Claims19

Dependent claims

An integrated circuit product, comprising:

a first transistor positioned in and above a first active region of a semiconducting substrate, wherein said first transistor comprises a first gate material stack and has a first gate length, said first gate material stack comprising a first gate dielectric layer having a first thickness positioned above said first active region and at least one layer of metal positioned above said first gate dielectric layer, wherein said first gate dielectric layer comprises a layer of a first high-k insulating material and a layer of a second high-k insulating material positioned on said layer of said first high-k insulating material;
and
a second transistor positioned in and above a second active region of said semiconducting substrate, wherein said second transistor comprises a second gate material stack and has a second gate length, said second gate material stack comprising a second gate dielectric layer having a second thickness positioned above said second active region and at least one layer of metal positioned above said second gate dielectric layer, wherein said second gate dielectric layer comprises a layer of said second high-k insulating material, said second gate length being less than said first gate length and said second thickness being less than said first thickness.

An integrated circuit product, comprising:

a first transistor positioned in and above a first active region of a semiconducting substrate, wherein said first transistor comprises a first gate structure and has a first gate length, said first gate structure comprising:
a first interfacial dielectric layer positioned on said first active region;
a first layer of high-k insulating material positioned on said first interfacial dielectric layer;
a second layer of high-k insulating material positioned on said first layer of high-k insulating material;
a first work function material layer positioned above said second layer of high-k insulating material;
and
a first conductive material layer positioned above said first work function material layer;
and
a second transistor positioned in and above a second active region of a semiconducting substrate, wherein said second transistor comprises a second gate structure and has a second gate length that is less than said first gate length, said second gate structure comprising:
a second interfacial dielectric layer positioned on said second active region;
a third layer of high-k insulating material positioned on said second interfacial dielectric layer;
a second work function material layer positioned above said third layer of high-k insulating material;
and
a second conductive material layer positioned above said second work function material layer.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/819,646Filed 6 Aug 2015 · division
Priority: 30 Jul 2012
Published: US 2015/0340362 A126 Nov 2015
Granted: 23 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

H10D 84/83
Of only field-effect components: of only insulated-gate FETs [IGFET]
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 64/01344
On single crystalline silicon, e.g. chemical oxidation using a liquid: in a nitrogen-containing ambient, e.g. N2O oxidation
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…

Family

Application13/561,315Parent of this division · filed 30 Jul 2012
US 2015/0340362 A1Pre-grant publication · published 26 Nov 2015
US 9,136,177 B2Parent of this division
US 2014/0027859 A1Published application
US 9,425,194 B2This patent

From the US filing history. Foreign family members aren’t listed.