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US 9,425,177 B2Granted
Method of manufacturing semiconductor device including grinding semiconductor wafer
AssigneeMicron Technology, Inc.
InventorsTadashi Koyanagi, Youkou Ito
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a semiconductor device according to one embodiment includes: preparing a semiconductor water which is partitioned into a plurality of first semiconductor chips, the plurality of first semiconductor chips including a first group of first semiconductor chips and a second group of first semiconductor chips; providing a second semiconductor chip over at least one of first semiconductor chips of the first group; providing a sealer on the first semiconductor chips of the second group; and grinding one face of the semiconductor wafer which is on the opposite side from a face on which the second semiconductor chip and the sealer are provided.
Claims28
A method of manufacturing a semiconductor device, the method comprising:
- preparing a semiconductor wafer which is partitioned into a plurality of first semiconductor chips, the plurality of first semiconductor chips including a first group of first semiconductor chips and a second group of defective semiconductor chips;
- positioning a plurality of second semiconductor chips over corresponding ones of the first semiconductor chips of the first group, but not over the defective semiconductor chips such that individual ones of the second semiconductor chips are separated from one another by individual voids over each of the defective semiconductor chips;
- disposing a sealer on a face of each of the defective semiconductor chips and such that the sealer fills the individual voids over each of the defective semiconductor chips;
- and
- grinding a face of the semiconductor wafer after the voids over each of the defective semiconductor chips are filled with the sealer, thereby reducing a variation in load applied to the semiconductor wafer during grinding.
2 more elements
A method of manufacturing a semiconductor device, the method comprising:
- preparing a semiconductor wafer which is partitioned into a plurality of first semiconductor chips;
- detecting a defective first semiconductor chip from among the plurality of first semiconductor chips;
- positioning a plurality second semiconductor chips in at least one tier on corresponding ones of the first semiconductor chips except for the defective first semiconductor chip such that individual ones of the second semiconductor chips are separated from one another by a void over the first defective semiconductor chip;
- disposing a sealer in the void and on a face of the defective first semiconductor chip;
- and
- grinding one face of the semiconductor wafer which is on the opposite side from a face in which the second semiconductor chips and the sealer are provided, wherein grinding the one face includes grinding the one face while the void over the first defective semiconductor chip is filled with the sealer to reduce a variation in load applied to the semiconductor wafer during grinding.
3 more elements
A method, comprising:
- preparing a semiconductor wafer including a first surface, a second surface opposite to the first surface and a plurality of first semiconductor chip regions formed in a side of the first surface;
- detecting a defective chip from among the plurality of first semiconductor chips, before stacking a plurality of second semiconductor chips;
- stacking the plurality of second semiconductor chips over the first semiconductor chips except for the defective chip, wherein each of the second semiconductor chips includes an upper surface;
- providing a sealing layer on the first surface of the semiconductor wafer with a sheet member being in contact with the upper surfaces of the second semiconductor chips, wherein the sealing layer is provided on the first surface of the semiconductor wafer so as to directly cover the defective chip and to fill a void that extends over the defective chip and between individual ones of the second semiconductor chips;
- and
- grinding the second surface of the semiconductor wafer, after providing the sealing layer.
3 more elements
A method comprising:
- providing an intermediate structure, the providing the intermediate structure comprising:
- preparing a wafer comprising a plurality of first semiconductor chips that are combined laterally with one another by a dicing line area, the plurality of first semiconductor chips including a plurality of non-defective chips and at least one defective chip, the at least one defective chip being between adjacent two of the non-defective chips;
- stacking a plurality of second semiconductor chips over the plurality of the non-defective chips, respectively, but not over the at least one defective chip such that a void is formed over the at least one defective chip;
- and
- forming a sealer such that the sealer fills the void over the at least one defective chip;
- and
- thinning the intermediate structure.
4 more elements
A method comprising:
- preparing a wafer comprising a plurality of first semiconductor chips that are combined laterally with one another by a dicing line area, wherein each of the plurality of first semiconductor chips is to be shipped if defectiveness is not detected therein;
- detecting whether each of the plurality of first semiconductor chips is non-defective or defective so that the wafer is modified such that the plurality of first semiconductor chips includes a plurality of non-defective chips and at least one defective chip;
- stacking a plurality of second semiconductor chips over the plurality of non-defective chips, respectively, but not over the at least one defective chip such that a void is formed over the at least one defective chip;
- forming a sealer such that the sealer fills the void over the at least one defective chip;
- and
- thinning the wafer after the void is filled with the sealer.
3 more elements
A method comprising:
- preparing a wafer, the wafer comprising a plurality of first semiconductor chips that are combined laterally with one another by a dicing line area, the plurality of first semiconductor chips including at least one defective chip and a plurality of non-defective chips, the at least one defective chip and the plurality of non-defective chips being equal in size to one another;
- stacking a plurality of second semiconductor chips over the plurality of non-defective chips, respectively, but not over the at least one defective chip such that a void is formed over the at least one defective chip;
- forming a sealer such that the sealer fills the void over the at least the defective chips;
- and
- grinding the wafer.
2 more elements
Dependencies are inferred from the claim text.