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US 9,425,157 B2Granted
Substrate and package structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu
Life of this patent
Estimating the term…
Abstract
According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
Claims17
A package structure, comprising:
- a chip, comprising a plurality of pillar bumps, each of the plurality of pillar bumps having a bump size;
- a substrate, having a first area and a second area, and comprising a plurality of pads, each of the plurality of pads having a pad size, wherein a ratio of the pad size to the bump size in the first area is larger than a ratio of the pad size to the bump size in the second area;
- and
- a plurality of solders, electrically connecting the plurality of pillar bumps and the plurality of pads.
1 more element
A substrate having a first area and a second area, comprising:
- a plurality of pillar bumps, each of the plurality of pillar bumps having a bump size;
- a plurality of pads, each of the plurality of pads having a pad size, wherein a ratio of the pad size to the bump size in the first area is larger than a ratio of the pad size to the bump size in the second area.
Dependencies are inferred from the claim text.