US 9,425,153 B2Granted

Semiconductor devices comprising getter layers and methods of making and using the same

AssigneeMonolith Semiconductor Inc.

InventorsKevin Matocha, John Nowak, Kiran Chatty, Sujit Banerjee

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Abstract

Semiconductor devices comprising a getter material are described. The getter material can be located in or over the active region of the device and/or in or over a termination region of the device. The getter material can be a conductive or an insulating material. The getter material can be present as a continuous or discontinuous film. The device can be a SiC semiconductor device such as a SiC vertical MOSFET. Methods of making the devices are also described. Semiconductor devices and methods of making the same comprising source ohmic contacts formed using a self-aligned process are also described. The source ohmic contacts can comprise titanium silicide and/or titanium silicide carbide and can act as a getter material.

Claims24

Dependent claims

A semiconductor device comprising:

a semiconductor substrate layer of a first conductivity type;
a drift layer of a semiconductor material of the first conductivity type on the substrate layer;
a first well region of a semiconductor material of a second conductivity type different than the first conductivity type in the drift layer in a central portion of the device;
a second well region of a semiconductor material of the second conductivity type in the drift layer and spaced from the first well region in the central portion of the device forming a JFET region between the first and second well regions;
a first source region of a semiconductor material of the first conductivity in the first well region and spaced from the JFET region such that an inner portion of the first well region is adjacent the JFET region;
a second source region of a semiconductor material of the first conductivity in the second well region and spaced from the JFET region such that an inner portion of the second well region is adjacent the JFET region;
a first outer region of semiconductor material of the second conductivity type adjacent the first source region opposite the JFET region;
a second outer region of semiconductor material of the second conductivity type adjacent the second source region opposite the JFET region;
a first gate dielectric layer on the drift layer and in contact with the inner regions of the first and second well regions and the JFET region;
a gate electrode on the first gate dielectric layer;
an interlayer dielectric material on the gate electrode, on the first and second source regions and on the first and second outer regions;
a first opening through the interlayer dielectric material over the first source region;
a second opening through the interlayer dielectric material over the second source region;
a first source ohmic contact on the first source region in the first opening;
and
a second source ohmic contact on the second source region in the second opening;
a source metal in electrical communication with the first and second source ohmic contacts.

14 more elements

A semiconductor device comprising:

a semiconductor substrate layer of a first conductivity type;
a drift layer of a semiconductor material of the first conductivity type on the substrate layer;
a first well region of a semiconductor material of a second conductivity type different than the first conductivity type in the drift layer in a central portion of the device;
a second well region of a semiconductor material of the second conductivity type in the drift layer and spaced from the first well region in the central portion of the device forming a JFET region between the first and second well regions;
a first source region of a semiconductor material of the first conductivity in the first well region and spaced from the JFET region such that an inner portion of the first well region is adjacent the JFET region;
a second source region of a semiconductor material of the first conductivity in the second well region and spaced from the JFET region such that an inner portion of the second well region is adjacent the JFET region;
a first outer region of semiconductor material of the second conductivity type adjacent the first source region opposite the JFET region;
a second outer region of semiconductor material of the second conductivity type adjacent the second source region opposite the JFET region;
a first gate dielectric layer on the drift layer and in contact with the inner regions of the first and second well regions and the JFET region;
a gate electrode on the first gate dielectric layer;
an interlayer dielectric material on the gate electrode, on the first and second source regions and on the first and second outer regions;
a first opening through the interlayer dielectric material over the first source region;
a second opening through the interlayer dielectric material over the second source region;
a first source ohmic contact on the first source region in the first opening;
and
a second source ohmic contact on the second source region in the second opening;
a source metal in electrical communication with the first and second source ohmic contacts;
wherein the semiconductor material is SiC;
and
wherein the first and second source ohmic contacts each comprise titanium-silicide and/or titanium-silicide-carbide.

17 more elements

A semiconductor device comprising:

a semiconductor substrate layer of a first conductivity type;
a drift layer of a semiconductor material of the first conductivity type on the substrate layer;
a first well region of a semiconductor material of a second conductivity type different than the first conductivity type in the drift layer in a central portion of the device;
a second well region of a semiconductor material of the second conductivity type in the drift layer and spaced from the first well region in the central portion of the device forming a JFET region between the first and second well regions;
a first source region of a semiconductor material of the first conductivity in the first well region and spaced from the JFET region such that an inner portion of the first well region is adjacent the JFET region;
a second source region of a semiconductor material of the first conductivity in the second well region and spaced from the JFET region such that an inner portion of the second well region is adjacent the JFET region;
a first outer region of semiconductor material of the second conductivity type adjacent the first source region opposite the JFET region;
a second outer region of semiconductor material of the second conductivity type adjacent the second source region opposite the JFET region;
a first gate dielectric layer on the drift layer and in contact with the inner regions of the first and second well regions and the JFET region;
a gate electrode on the first gate dielectric layer;
an interlayer dielectric material on the gate electrode, on the first and second source regions and on the first and second outer regions;
a first opening through the interlayer dielectric material over the first source region;
a second opening through the interlayer dielectric material over the second source region;
a first source ohmic contact on the first source region in the first opening;
a second source ohmic contact on the second source region in the second opening;
a source metal in electrical communication with the first and second source ohmic contacts;
a getter material on the interlayer dielectric material;
a getter material on the first source ohmic contact in the first opening;
and
a getter material on the second source ohmic contact in the second opening;
wherein the getter material comprises Ti and TiN.

18 more elements

A semiconductor device comprising:

a semiconductor substrate layer of a first conductivity type;
a drift layer of a semiconductor material of the first conductivity type on the substrate layer;
a first well region of a semiconductor material of a second conductivity type different than the first conductivity type in the drift layer in a central portion of the device;
a second well region of a semiconductor material of the second conductivity type in the drift layer and spaced from the first well region in the central portion of the device forming a JFET region between the first and second well regions;
a first source region of a semiconductor material of the first conductivity in the first well region and spaced from the JFET region such that an inner portion of the first well region is adjacent the JFET region;
a second source region of a semiconductor material of the first conductivity in the second well region and spaced from the JFET region such that an inner portion of the second well region is adjacent the JFET region;
a first outer region of semiconductor material of the second conductivity type adjacent the first source region opposite the JFET region;
a second outer region of semiconductor material of the second conductivity type adjacent the second source region opposite the JFET region;
a first gate dielectric layer on the drift layer and in contact with the inner regions of the first and second well regions and the JFET region;
a gate electrode on the first gate dielectric layer;
an interlayer dielectric material on the gate electrode, on the first and second source regions and on the first and second outer regions;
a first opening through the interlayer dielectric material over the first source region;
a second opening through the interlayer dielectric material over the second source region;
a first source ohmic contact on the first source region in the first opening;
a second source ohmic contact on the second source region in the second opening;
a source metal in electrical communication with the first and second source ohmic contacts;
a first plug on the first getter material on the first ohmic contact in the first opening;
and
a second plug on the second getter material on the second ohmic contact in the second opening;
wherein the source metal is on the first and second plugs;
and
wherein the first and second plugs each comprise tungsten.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/680,766Filed 7 Apr 2015 · continuation in part
Priority: 4 Apr 2013
Published: US 2015/0214164 A130 Jul 2015
Granted: 23 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification31 codes

H10W 76/48
Fillings: fillings including materials for absorbing or reacting with moisture or other undesired substances
H10D 12/031
Manufacture or treatment: of igbts
H10D 12/032
Of igbts: of vertical IGBTs
H10D 12/441
Insulated-gate bipolar transistors [IGBT]: vertical IGBTs

Family

Application61/808,332Us provisional application · filed 4 Apr 2013
Application14/245,172Parent of this continuation-in-part · filed 4 Apr 2014
US 2015/0214164 A1Pre-grant publication · published 30 Jul 2015
US 9,035,395 B2Parent of this continuation-in-part
US 2014/0299887 A1Published application
US 9,425,153 B2This patent

From the US filing history. Foreign family members aren’t listed.