US 9,425,150 B2Granted

Multi-via interconnect structure and method of manufacture

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsYu-Fei Huang, Ming Xiang Li, Edward Wan, Jacob Chen, Dun-Nian Yaung, Cheng-Eng Daniel Chen

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Abstract

An interconnect structure and a method of forming the interconnect structure are provided. Two wafers (and/or dies) are bonded together. A multi-via interconnect structure is formed extending from a backside of a first substrate to interconnect structures in the metallization layers on the first integrated circuit and the second integrated circuit. The multi-via interconnect structure may be formed by thinning a first substrate of a first wafer and forming a first opening through the first substrate. A second opening extends from the first opening to a first interconnect structure on the first wafer, and a third opening extends from the first interconnect structure on the first wafer to a second interconnect structure on the second wafer. The first, second, and third openings are filled with a conductive material, thereby forming a multi-via interconnect structure.

Claims20

Dependent claims

A method comprising:

providing a bonded structure having a first semiconductor chip having a first substrate bonded to a second semiconductor chip having a second substrate, the first substrate having one or more first dielectric layers thereon and a first pad in the one or more first dielectric layers, the second substrate having one or more second dielectric layers thereon and a second pad in the one or more second dielectric layers, the first substrate being bonded to the second substrate such that the first dielectric layers face the second dielectric layers, wherein the first semiconductor chip is a first technology node chip and the second semiconductor chip is a second technology node chip, the first technology node chip being a different technology node than the second technology node chip;
forming a first opening extending through the first substrate;
forming a second opening extending from the first opening to the first pad;
forming a third opening extending from the first pad to the second pad;
and
simultaneously forming a first multi-via interconnect structure and a redistribution layer with a conductive material, wherein the first multi-via interconnect structure is formed in the first opening, the second opening, and the third opening, wherein the redistribution layer provides an external electrical connection to the first multi-via interconnect structure.

3 more elements

A method comprising:

forming a first opening and a second opening in a bonded structure, the bonded structure having a first substrate and a second substrate, the first substrate having one or more first dielectric layers thereon, the one or more first dielectric layers having a first pad and a second pad therein, the second substrate having one or more second dielectric layers thereon, the one or more second dielectric layers having a third pad and a fourth pad therein, the first substrate being bonded to the second substrate such that the first dielectric layers face the second dielectric layers, electrical circuitry on the first substrate and the second substrate being different nodes, the first opening and the second opening extending through the first substrate, the first pad being electrically isolated from electrical circuitry on the first substrate;
forming a third opening extending from the first opening to the first pad;
forming a fourth opening extending from the second opening to the second pad;
forming a fifth opening extending from the first pad to the third pad;
forming a sixth opening extending from the second pad to the fourth pad;
forming a first multi-via interconnect structure in the first opening, third opening, and the fifth opening;
and
forming a second multi-via interconnect structure in the second opening, fourth opening, and the sixth opening;
covering the first multi-via interconnect structure and the second multi-via interconnect structure with a dielectric layer;
and
exposing the second multi-via interconnect structure, the first multi-via interconnect structure remaining covered.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/257,759Filed 21 Apr 2014 · us provisional application
Priority: 13 Feb 2014
Published: US 2015/0228584 A113 Aug 2015
Granted: 23 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10W 70/611
Insulating or insulated package substrates; Interposers; Redistribution layers: for connecting multiple chips together
H10W 20/023
Of interconnections within wafers or substrates: the interconnections being through-semiconductor vias
H10W 20/0234
The interconnections being through-semiconductor vias: comprising etching via holes that stop on pads or on electrodes
H10W 20/0238
The interconnections being through-semiconductor vias: comprising etching via holes through pads or through electrodes