Semiconductor devices having contacts with intervening spacers and method for fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHo-Jun Kim, Hae-Wang Lee, Chul-Hong Park, Dong-Kyun Sohn, Jong-Shik Yoon
Life of this patent
Estimating the term…
Abstract
Semiconductor devices, and a method for fabricating the same, include an interlayer dielectric film pattern over a substrate, a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, a second wiring within the interlayer dielectric film pattern and separated from the first wiring, and a spacer contacting the first wiring and the second wiring. The spacer electrically separates the first wiring and the second wiring from each other. The second wiring has a second length different from the first length in the first direction.
Claims20
A semiconductor device, comprising:
- an interlayer dielectric film pattern over a substrate;
- a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, the first wiring including a first sidewall and a second sidewall opposing each other;
- a second wiring within the interlayer dielectric film pattern and separated from the first wiring,
- the second wiring having a second length different from the first length in the first direction,
- the second wiring including a third sidewall and a fourth sidewall opposing each other, and
- an upper surface of the first wiring being coplanar with an upper surface of the second wiring;
- and
- a spacer contacting the first wiring and the second wiring,
- the spacer electrically separating the first wiring and the second wiring from each other and being made of an etching resistant material different from the interlayer dielectric film pattern,
- the spacer being disposed between the first sidewall and the third sidewall, and on the second sidewall,
- the spacer not being disposed on the fourth sidewall, and
- the upper surface of the first wiring, the upper surface of the second wiring and an upper surface of the spacer are formed at a same level.
A semiconductor device, comprising:
- first patterns arranged on a substrate along a same longitudinal axis in a first direction,
- a second pattern on the substrate adjacent to the first patterns;
- an interlayer dielectric film pattern including a first opening and a second opening over the first patterns and the second pattern, respectively;
- a first wiring and a second wiring filling the first opening and the second opening, respectively,
- the first wiring extending over the substrate in the first direction, and
- opposing ends of the first wiring extending over a respective one of the first patterns in the first direction;
- and
- a spacer between a side upper portion of the first wiring and a side upper portion of the second wiring, the spacer separating the first wiring and the second wiring from each other,
- wherein the first patterns are electrically connected by the first wiring, and the first wiring is on the first patterns, and
- an upper surface of the first wiring, an upper surface of the second wiring and an upper surface of the spacer are formed at a same level.
A semiconductor device, comprising:
- a first contact pattern and a second contact pattern each traversing different active regions of a substrate;
- a third contact pattern on the substrate, the first and second contact patterns extending along a same side of the third contact pattern;
- an interlayer dielectric film pattern over the first, second and third contact patterns;
- and
- a multi-wiring structure extending through the interlayer dielectric film pattern, the multi-wiring structure including a first wiring and a second wiring separated from each other and a spacer adjoined to the first and second wirings,
- the first wiring being parallel with the third contact pattern,
- the first wiring being on and electrically connected to the first and second contact patterns, and
- the second wiring being electrically connected to the third contact pattern, and
- an upper surface of the first wiring, an upper surface of the second wiring, and an upper surface of the spacer being formed at a same level.
A semiconductor device, comprising:
- an interlayer dielectric film pattern over a substrate;
- a first wiring within the interlayer dielectric film pattern and having a first length in a first direction, the first wiring including a first sidewall and a second sidewall opposing each other;
- a second wiring within the interlayer dielectric film pattern and separated from the first wiring,
- the second wiring having a second length different from the first length in the first direction;
- and
- the second wiring including a third sidewall and a fourth sidewall opposing each other;
- and
- a spacer contacting the first wiring and the second wiring,
- the spacer electrically separating the first wiring and the second wiring from each other and being made of an etching resistant material different from the interlayer dielectric film pattern,
- the spacer being disposed between the first sidewall and the third sidewall, and on the second sidewall,
- the spacer including a first portion on an uppermost portion of the first sidewall, and a second portion between the second sidewall and the third sidewall,
- the first portion not contacting the first sidewall below the uppermost portion of the first sidewall, and
- the spacer not being disposed on the fourth sidewall.
Dependencies are inferred from the claim text.