Chip package

A chip package, comprising:

• a chip having an upper surface, a lower surface and a sidewall, wherein the chip comprises a sensing region or device region and a signal pad region adjacent to the upper surface;
• a shallow recess structure outside of the signal pad region and extending from the upper surface toward the lower surface along the sidewall, wherein the shallow recess structure has at least a first recess and a second recess under the first recess;
• a redistribution layer electrically connected to the signal pad region and extending into the shallow recess structure;
• a wire having a first end and a second end, wherein the first end is disposed in the shallow recess structure and electrically connected to the redistribution layer, and the second end is used for external electrical connection, wherein the chip comprises a semiconductor substrate and an insulating layer, a first sidewall of the first recess adjoins the insulating layer and a second sidewall of the second recess adjoins the semiconductor substrate, wherein a first bottom of the first recess exposes a surface of the semiconductor substrate, and the signal pad region is separated from the semiconductor substrate by the insulating layer;
• and wherein the first end of the wire is located at the first bottom of the first recess;
• and
• an encapsulant layer at least covering the wire.

A chip package, comprising:

• a chip having an upper surface, a lower surface and a sidewall, wherein the chip comprises a sensing region or device region and a signal pad region adjacent to the upper surface;
• a shallow recess structure outside of the signal pad region and extending from the upper surface toward the lower surface along the sidewall, wherein the shallow recess structure has at least a first recess and a second recess under the first recess;
• a redistribution layer electrically connected to the signal pad region and extending into the shallow recess structure;
• a wire having a first end and a second end, wherein the first end is disposed in the shallow recess structure and electrically connected to the redistribution layer, and the second end is used for external electrical connection, and wherein the first end of the wire is located at a bottom of the first recess;
• and
• an encapsulant layer at least covering the wire.

A chip package, comprising:

• a chip having an upper surface, a lower surface and a sidewall, wherein the chip comprises a sensing region or device region and a signal pad region adjacent to the upper surface;
• a shallow recess structure outside of the signal pad region and extending from the upper surface toward the lower surface along the sidewall, wherein the shallow recess structure has at least a first recess and a second recess under the first recess;
• a redistribution layer electrically connected to the signal pad region and extending into the shallow recess structure;
• a wire having a first end and a second end, wherein the first end is disposed in the shallow recess structure and electrically connected to the redistribution layer, and the second end is used for external electrical connection, wherein the first end of the wire is located at a bottom of the first recess, and wherein a portion of the wire is higher than the upper surface of the chip;
• and
• an encapsulant layer at least covering the wire.