Package structure and fabrication method thereof

A method for fabricating a package structure, comprising the steps of:

• preparing a first wafer, a chip disposed on the first wafer, and a lid member disposed on the chip, wherein the first wafer has opposite first and second surfaces and the first surface of the first wafer has a groove, a thin film closing an open end of the groove and a plurality of electrical contacts, and the chip has a third surface with a plurality of electrode pads and an opposite fourth surface with a concave portion and a seal ring located at a periphery of the concave portion, such that the chip is disposed on the first surface of the first wafer in a manner that the seal ring surrounds the thin film of the first wafer and the electrical contacts are located outside the seal ring, and the lid member is disposed on the third surface of the chip and has a conductive layer formed on a top surface thereof;
• electrically connecting the electrical contacts of the first wafer and the conductive layer of the lid member through a plurality of first conductive wires, and electrically connecting the electrical contacts of the first wafer and the electrode pads of the chip through a plurality of second conductive wires;
• forming an encapsulant on the first surface of the first wafer for encapsulating the chip, the lid member, the electrical contacts, the first conductive wires and the second conductive wires;
• removing a portion of the encapsulant and a portion of the first conductive wires from a top surface of the encapsulant so as to form a plurality of sub-conductive wires, wherein one ends of the sub-conductive wires are exposed from the encapsulant and the other ends of the sub-conductive wires are in electrical connection with the electrical contacts of the first wafer;
• and
• forming a through hole penetrating the first surface and the second surface of the first wafer and communicating with the concave portion of the chip.

A package structure, comprising:

• a wafer having opposite first and second surfaces, wherein the first surface of the wafer has a groove, a thin film closing an open end of the groove, and a plurality of electrical contacts, and wherein the thin film is coplanar with the first surface, and the groove is in a vacuum state;
• a chip disposed on the first surface of the wafer, wherein the chip has a third surface with a conductive layer and an opposite fourth surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the first surface of the wafer in a manner that the seal ring surrounds the thin film of the wafer and the electrical contacts are located outside the seal ring;
• an encapsulant formed on the first surface of the wafer for encapsulating the chip and the electrical contacts;
• a plurality of sub-conductive wires embedded in the encapsulant, wherein one ends of the sub-conductive wires are exposed from a top surface of the encapsulant and the other ends of sub-conductive wires are in electrical connection with the electrical contacts of the wafer;
• and
• a through hole penetrating the first surface and the second surface of the wafer and communicating with the concave portion of the chip.

A package structure, comprising:

• a wafer having opposite first and second surfaces, wherein the first surface of the wafer has a groove, a thin film closing an open end of the groove, and a plurality of electrical contacts, and wherein the thin film is coplanar with the first surface, and the groove is in a vacuum state;
• a chip disposed on the first surface of the wafer, wherein the chip has a third surface with a plurality of electrode pads and an opposite fourth surface with a concave portion and a seal ring located at a periphery of the concave portion, the chip being disposed on the first surface of the wafer in a manner that the seal ring surrounds the thin film of the wafer and the electrical contacts are located outside the seal ring;
• a lid member disposed on the third surface of the chip and having a conductive layer formed on a top surface thereof;
• an encapsulant formed on the first surface of the wafer for encapsulating the chip and the electrical contacts;
• a plurality of sub-conductive wires embedded in the encapsulant, wherein one ends of the sub-conductive wires are exposed from a top surface of the encapsulant and the other ends of sub-conductive wires are in electrical connection with the electrical contacts of the wafer;
• a plurality of conductive wires embedded in the encapsulant for electrically connecting the electrical contacts of the wafer and the electrode pads of the chip;
• and
• a through hole penetrating the first surface and the second surface of the wafer and communicating with the concave portion of the chip.