Calibration kits for RF passive devices

A method comprising:

• designing a plurality of calibration kits from a design specification, wherein the design specification comprises:
• a first specification of a passive device;
• a second specification for routing metal lines in dielectric layers that are under the passive device, wherein the routing metal lines are overlapped by the passive device;
• and
• a third specification of pattern densities of the routing metal lines;
• manufacturing a chip comprising the plurality of calibration kits, wherein each of the plurality of calibration kits comprises the passive device, wherein the passive devices in the plurality of calibration kits are identical to each other, and wherein all routing metal lines in combination in each of the plurality of calibration kits and overlapped by the respective one of the plurality of calibration kits are different from all routing metal lines in combination in any other one of the plurality of calibration kits;
• and
• measuring the plurality of calibration kits to generate a first plurality of performance data, wherein the measuring the plurality of calibration kits is performed using a three-step de-embedding method, and the three-step de-embedding method comprises:
• measuring a short device having first test pads shorted with each other;
• measuring an open device having second test pads disconnected from each other, wherein the second test pads are identical to the first test pads;
• and
• measuring a through-device comprising third test pads and the passive device in a respective one of the plurality of calibration kits connected between the third test pads, wherein the third test pads are identical to the first test pads.

A device comprising:

• a chip comprising:
• a substrate;
• and
• a plurality of dielectric layers over the substrate;
• a first calibration kit in the chip, wherein the first calibration kit comprises:
• a first passive device over the plurality of dielectric layers, wherein substantially no metal feature is disposed in the plurality of dielectric layers and overlapped by the first passive device;
• and
• a second calibration kit in the chip, wherein the second calibration kit comprises:
• a second passive device over the plurality of dielectric layers, wherein the second passive device is identical to the first passive device, wherein each of the first and the second calibration kits comprises one or more test pads connected to the respective first passive device and the second passive device;
• and
• first dummy patterns in the plurality of dielectric layers and overlapped by the second passive device, wherein the first dummy patterns are electrically floating.