Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsJin-Woo Park, Ji Hwang Kim, Jongbo Shim
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a package substrate; a semiconductor chip mounted on a top surface of the package substrate; a chip pad disposed on a bottom surface of the semiconductor chip to face the top surface of the package substrate, the chip pad including a connection pad and a measurement pad; and a chip bump including a first bump provided between the package substrate and the connection pad and a second bump provided between the package substrate and the measurement pad. An interconnection disposed within the package substrate is not connected to the second bump to be electrically isolated from the second bump.
Claims20
A semiconductor package comprising:
- a package substrate;
- a semiconductor chip on a top surface of the package substrate;
- a chip pad on a bottom surface of the semiconductor chip to face the top surface of the package substrate, the chip pad including a connection pad and a measurement pad;
- and
- a chip bump including a first bump between the package substrate and the connection pad and a second bump between the package substrate and the measurement pad,
- wherein an interconnection within the package substrate is not connected to the second bump to be electrically isolated from the second bump.
A semiconductor package comprising:
- a package substrate;
- a semiconductor chip mounted on a top surface of the package substrate;
- chip pads disposed on a bottom surface of the semiconductor chip to face the top surface of the package substrate, the chip pads including connection pads and measurement pads;
- and
- first bumps provided between the package substrate and the connection pads,
- wherein second bumps are attached onto some of the measurement pads and are not attached onto others of the measurement pads.
Dependencies are inferred from the claim text.