Yield enhancing vertical redundancy method for 3D wafer level packaged (WLP) integrated circuit systems

A wafer level package comprising:

• a first wafer substrate including a first surface and a second surface;
• a second wafer substrate including a first surface and a second surface, said first wafer substrate being bonded to the second wafer substrate and defining a cavity therebetween;
• a first integrated circuit fabricated on the second surface of the first substrate and positioned within the cavity;
• a second integrated circuit fabricated on the first surface of the second substrate and positioned within the cavity where one of the first and second integrated circuits is designated as an active circuit and the other of the first and second integrated circuits is designated as an inactive circuit, wherein the first and second integrated circuits are redundant circuits and include the same circuit components;
• and
• a metal blanket layer deposited over the inactive circuit so as to make the inactive circuit inoperable.

A method for fabricating a three-dimensional wafer level package including vertically redundant integrated circuits, said method comprising:

• providing a plurality of wafer substrates;
• fabricating a plurality of integrated circuits on each of the wafer substrates;
• testing a performance of each of the integrated circuits on all of the wafer substrates;
• generating a wafer map for each of the wafer substrates based on the performance test for each of the integrated circuits on each wafer substrate that identifies each circuit as being an operable active circuit or an inoperable inactive circuit based on its performance;
• pairing two or more wafer substrates together based on their respective wafer maps to optimize a yield of pairs of vertically opposed circuits where an optimized number of pairs of integrated circuits includes at least one active circuit;
• processing each integrated circuit on each wafer based on the wafer-to-wafer pairing so that the active circuits include active circuit connections and the inactive circuits include a metallization layer that short circuits components in the inactive circuit;
• and
• providing wafer-to-wafer bonding of the wafer substrates that have been paired together so that vertically opposed active and inactive integrated circuits are positioned within a cavity between the wafer substrates.