Semiconductor device including self-aligned gate structure and improved gate spacer topography

A semiconductor device, comprising:

• at least one semiconductor fin on an upper surface of a semiconductor substrate;
• at least one metal gate stack formed on the upper surface of the semiconductor substrate;
• and
• at least one pair of opposing source/drain contact structures formed on the upper surface of the semiconductor fin, each source/drain contact structure comprising:
• a metal contact stack atop the upper surface of the at least one fin;
• a first spacer interposed between a contact sidewall of the metal contact stack and a gate sidewall of the at least one metal gate stack, and a second spacer opposite the first spacer, the second spacer interposed between the metal contact stack and a dielectric layer on a portion of the at least one fin;
• and
• a cap spacer formed on an upper surface of the metal contact stack and having a cap portion including first and second opposing side portions extending perpendicularly from the cap spacer, the first side portion disposed against the first spacer and the second side portion disposed against the second spacer,
• wherein the metal gate stack is interposed between the opposing source/drain contact structures.